獵速科技股份有限公司

半導體IC設計
  • 公司規模
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公司簡介

本公司創立至今,本著提供良好的品質及專業的態度,給予客戶最好的產品,秉持著穩健發展、追求企業永續經營及成長為理念,我們重視每一位員工,除了有良好工作環境、也提供學習及成長的空間,歡迎優秀的朋友一起加入我們的工作行列。

At Teletrx, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Teletrx is the right place for you! At Teletrx we care deeply about creating meaningful development experiences while building a strong sense of belonging and connection. We foster an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. 

公司位置

獵速科技股份有限公司

獵速科技股份有限公司 工作機會(2)

  • 11/24
    面議(經常性薪資4萬/月含以上)
    • 週休二日
    • 日班
    1.設計數位或類比電路。 2.模擬電路。 3.整理相關研究報告。 4.量測晶片。
  • 11/24
    月薪 100,000元 以上
    • 週休二日
    • 日班
    Qualifications • Strong knowledge of analog CMOS designs and topologies. • Experience with high speed digital circuit (e.g., serializer, deserializer, counters, dividers, etc.) design, analysis and verification. • Experience in analyzing link jitter budget for high-speed serial links and creating block level requirements. • Knowledge of different PLL/CDR architectures. • Experience with PLL/CDR design including building blocks (VCO, charge pump, divider, etc. • Modeling of CDR and adaptive loops (using C, Matlab or Python, etc.). • Knowledge of ESD requirements. • MS with 3+ year experience working on high speed SERDES circuits in advanced CMOS process nodes. • Experience in designing op-amps, band gaps, differential amplifiers, LDO • Architecture experience with transceiver equalizers (TX FIR, RX analog FFE, CTLE, and DFE) – DSP (FFE and DFE) experience is preferred • Strong understanding of signal integrity and EM issues, especially related to serdes channel modelling. • Experience with mixed-mode simulation of analog and digital blocks, including behavioral modeling of analog circuits, using tools like verilog or verilogA for simulation. • Experience with synthesized digital design flows, using RTL descriptions to synthesize verified netlists for physical implementation. • Full-custom analog layout techniques and the ability to take a design and do all the layout extract verification and sign-off. • Working experience with high speed NRZ and PAM4 Serdes, PLLs, CDR and FEC. • In depth knowledge of the IEEE 802.3 and OIF specifications for 25Gbps and 56Gbps Serdes Interfaces. • Working knowledge of system level power integrity and budgeting (DC, AC, transient analysis). • Experience of IC mass production 月薪可面議
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