• Strong knowledge of analog CMOS designs and topologies.
• Experience with high speed digital circuit (e.g., serializer, deserializer, counters, dividers, etc.) design, analysis and verification.
• Experience in analyzing link jitter budget for high-speed serial links and creating block level requirements.
• Knowledge of different PLL/CDR architectures.
• Experience with PLL/CDR design including building blocks (VCO, charge pump, divider, etc.
• Modeling of CDR and adaptive loops (using C, Matlab or Python, etc.).
• Knowledge of ESD requirements.
• MS with 3+ year experience working on high speed SERDES circuits in advanced CMOS process nodes.
• Experience in designing op-amps, band gaps, differential amplifiers, LDO
• Architecture experience with transceiver equalizers (TX FIR, RX analog FFE, CTLE, and DFE) – DSP (FFE and DFE) experience is preferred
• Strong understanding of signal integrity and EM issues, especially related to serdes channel modelling.
• Experience with mixed-mode simulation of analog and digital blocks, including behavioral modeling of analog circuits, using tools like verilog or verilogA for simulation.
• Experience with synthesized digital design flows, using RTL descriptions to synthesize verified netlists for physical implementation.
• Full-custom analog layout techniques and the ability to take a design and do all the layout extract verification and sign-off.
• Working experience with high speed NRZ and PAM4 Serdes, PLLs, CDR and FEC.
• In depth knowledge of the IEEE 802.3 and OIF specifications for 25Gbps and 56Gbps Serdes Interfaces.
• Working knowledge of system level power integrity and budgeting (DC, AC, transient analysis).
• Experience of IC mass production