工作項目： 負責下列工作項目之一 1. Digital Verification Flow. (1) RTL signoff for Lint/CDC/RDC/Constraint. (2) Formal/Simulation/Equivalence checking. (3) Power analysis/optimization、Low power verification. 2. Digital Implementation Flow. (1) High performance/high congestion core synthesis. (2) Advanced-process nodes STA analysis. 3. Characterization and Signoff Margining Flow. (1) Standard/memory cell characterization and circuit exploration. (2) Timing signoff margining analysis and calibration. 應徵條件： 1. 碩士以上；電機、電機與控制、電信、電子、資工、資訊相關科系畢業為佳。 2. 具備3年以上相關工作經驗為佳。 3. 熟悉 Linux工作環境以及 TCL/Perl/Shell script. 4. 熟悉 Front-end Design Implementation EDA Tool.

工作項目： 1. ARM Architecture based Complex CPU Subsystem Platform Design & Integration, Add-on Features Enablement and IP Development 2. SoC Architecture Exploration, Performance Projection and Bottleneck Analysis 3. Benchmark/Power Characterization on Emulation Platform, Result Analysis and Optimization 4. CPU Architecture/Micro-architecture Research 5. Involvement of Post-silicon Bring-up and Debug 應徵條件： 1.碩士以上；電機、資工、電子相關科系畢業為主。 2.具IP開發經驗，熟悉 SoC Integration & Design Flow、Frontend Timing/Power Analysis EDA Tools。 3.熟悉ARMv7/v8-A CPU 架構及AMBA protocol，有 ARM Cortex-A CPU/Subsystem Design/Integration/PPA Optimization/Sign-off 經驗尤佳。 4.具Emulation platform (Zebu, Palladium)經驗尤佳。 5.有 Low Power Design & Verification、Post-Silicon Validation & Debug 經驗尤佳。 6.積極負責、溝通協調能力強、勇於迎接挑戰，對於 High-Performance CPU Technology 有興趣者。電機工程學類,電子工程學類,資訊工程學類

Job Description： 1. Locate in Seoul, Korea. 2. Provide pre-sales and post-sales support. 3. Understand customer requirements, and deliver technical presentations, reports, documents, and technology demonstrations. 4. Support customer product development and design. 5. Support customer issue analysis and resolution. 6. On-site support for debugging or certification tests. 7. Cross-functional collaboration with Realtek internal resources. Education, Skills, Abilities, And Experience Required： • M.S. or B.S. in Electrical Engineering or equivalent. • Fluent in Korean language verbally and in written. • 3 to 5 years of progressive professional technical experience in IC design or related areas, direct experience in IC design house FAE is preferred. • Strong analytical and problem-solving skills. • Strong written/verbal communication and negotiation skills. • SoC/MCU FW programming skill is a plus • Tool SW utility experience is a plus • Being proactive and willing to take initiative. • Ability to work independently to achieve goals. • Ability to understand and explain technical issues and solutions to technical and non-technical personnel. • Medium or higher English skills. • Familiarity with Ethernet protocols will be a plus. • Familiarity with the Automotive ecosystem will be a plus. • Basic or higher Chinese skills will be a plus. • Experience of Linux will be a plus Industry： Automotive Ethernet, Semiconductor Job Functions： Engineering, Business Development電機工程學類,電子工程學類,通信學類

應徵條件： 1. 瑞昱強力招募(1)113年度研發替代役及(2)預聘113年應屆畢業之碩士、博士生。 2. 碩士以上之電子、電機、電信、電控、資工、資科等相關科系，並具下列任一條件者佳： a. 熟悉數位信號處理、數位通信系統。 b. 熟悉於影像系統或數位影像處理，或影像壓縮/解壓縮演算法。 c. 熟悉計算機架構或對SoC設計有興趣者。 d. 具有電路設計、製程整合、元件經驗或有興趣者。 e. 熟悉HDL設計。 f. 對通訊網路、聯網多媒體、多媒體、電腦週邊、車用電子產品或程式設計有濃厚興趣者。電機工程學類,電子工程學類,通信學類

應徵條件： 1. 瑞昱強力招募(1)113年度研發替代役及(2)預聘113年應屆畢業之碩士、博士生。 2. 碩士以上；電機、資訊等相關科系，並具下列任一條件者佳： a. 熟悉Verilog RTL、Synthesis、Simulation、Timing Analysis 等相關 IC Design Flow及有興趣者。 b. 熟悉 Design for Testability 技術，包含 Scan / ATPG、Delay Test、Memory BIST、Boundary Scan、Diagnosis 等及有興趣者。 c. 有 DFT Tools (如 DFT Compiler、TetraMAX、BSD Compiler、FastScan、TestKompress、MBISTArchitect) 使用經驗及有興趣者。 d. 積極負責、勇於迎接挑戰，對於 Nanometer / SoC DFT Implementation、開發及推廣設計流程有興趣者。電機工程學類,電子工程學類,資訊工程學類

工作項目： 負責下列工作項目之一 1. Fully Layout environment and flow build-up. 2. In-house Layout automatic utility development. 3. In-house PDK development. 4. Project layout and process migration supporting. 應徵條件： 1. 大學以上；電機、電機與控制、電信、電子、資工、資訊相關科系畢業為佳。 2. 具備3年以上 Fully Custom Layout 相關工作經驗為佳。 3. 熟悉 Linux工作環境以及 TCL/Perl/Shell script/Skill Language. 4. 熟悉 Fully Custom Layout EDA Tool.通信學類,電機工程學類,電子工程學類

工作項目： 1. Maintain並開發 USB3、USB4與 PCIe之 DPHY/MAC相關 design. 2. 整合 USB3、USB4、PCIe等 SerDes PHY與 MAC. 應徵條件： 1. 熟悉 USB3.2、PCIe、PIPE4/5等 Spec. 2. 具 USB3.2 or PCIe Gen3/Gen4 DPHY/MAC設計經驗。 3. 具 USB3.2 or PCIe Gen3/Gen4等 PHY IP整合經驗。 4. 具備 SoC晶片整合能力。

1. Hardware System Design。 2. FPGA Design。 3. 撰寫IC設計開發軟體。電機工程學類,電子工程學類

1. Summary Realtek Semiconductor Corp., located in the Hsinchu Science-based Industrial Park, Taiwan‘s 〝Silicon Valley〝, established in 1987. Realtek‘s efforts to provide the ultimate in pioneering IC technology — along with its firm commitment to creating unique and innovative designs for a broad range of high-tech applications — have won the company a worldwide reputation and made possible a favorable and consistent growth rate in the years since its establishment. In line with the Realtek culture of 〝Self-confidence and trust in people〝, we believe that we can achieve our best, and trust our colleagues can also do the same. Working and learning in Realtek, we openly share knowledge and experience with one another to inspire innovation and pursue growth of the company, as well the individuals. Talent is the important capital of Realtek. Welcome to Join Realtek Family! 2. Essential Job Functions ‧Locate in Southern part of Germany (Frankfurt to Stuttgart, or Stuttgart to Munich) ‧Provide pre-sales and post-sales support. ‧Understand customer requirements, and deliver technical presentations, reports, documents and technology demonstrations. ‧Support customer product development and design. ‧Support customer issue analysis and resolve. ‧On-site support for debug or certification test. ‧Cross-functional collaboration with Realtek internal resources. 3. Education, Skills, Abilities, And Experience Required ‧M.S. or B.S. in Engineering or equivalent. ‧3 to 5 years of progressive professional technical experience in IC design or related areas, direct experience in IC design house FAE is preferred. ‧Strong analytical and problem solving skills. ‧Strong written/verbal communication and negotiation skills. ‧Being proactive and willing to take initiatives. ‧Ability to work independently to achieve goals. ‧Ability to understand and explain technical issues and solutions to technical and non-technical personnel. ‧Native German skill. ‧Medium or higher English skill. ‧Familiar with Ethernet protocols will be a plus. ‧Familiar with Automotive ecosystem will be a plus. ‧Basic or higher Chinese skill will be a plus. ‧Experience of Linux system will be a plus. 4. Industry Automotive Ethernet, Semiconductor 5. Employment Type Full-time 6. Job Functions Engineering, Business Development電機工程學類,電子工程學類,通信學類

1.數位電路設計 2.HDL coding(VHDL / Verilog) 3.電路圖繪製Orcad 4.測試程式撰寫 5.產品量產技術移轉電機工程學類,電子工程學類,資訊工程學類

工作項目： 1. SoC bus architecture 架構設計。 2. 平台效能分析與改善。 應徵條件： 1. 碩士以上; 電機工程、電信工程、電控工程、電子工程、資訊工程、資訊科學、動力機械、自動控制、通訊工程等相關科系畢業為主。 2. 具2年以上 SoC系統架構設計, 或有 DDR controller設計相關經驗者為佳。電子工程學類,電機工程學類,資訊工程學類

1. 熟悉FPGA (XILINX/ALTERA)設計。 2. 數位電路設計、驗證與模擬。 3. 影像系統或數位影像處理演算法設計與實現。 ***歡迎應屆畢業生投履歷***

1. FPGA邏輯電路設計與實現。 2. 影像演算法設計與實現。電機工程學類,電子工程學類,資訊工程學類

Job function: 1. Work with Digital Design team for Physical Design of SoC chips including top level floor planning, block partition, timing budgeting, power planning, block integration, whole chip timing closure, and tape out. 2. Responsible for physical design methodology research and development. 3. Cross site projects coordination and management. Requirement: 1. MS with 5+ years of experience in Physical Design. 2. Familiar with Unix/Linux environment and scripts. 3. Familiar with ASIC design flow. 4. Familiar with Physical Design EDA tools. 5. Good communication and team working skills. 6. Experience in handling large scale SoC chip implementation is a plus.

工作項目： Audio/Speech signal processing(Algorithm), Architecture Design and RTL Coding. 應徵條件： 1. 碩士以上; 電子、電機、資工、電信、電控、資科等相關科系畢業為主。 2. 具相關工作經驗者為佳。電機工程學類,電子工程學類,通信學類

工作項目： DDR3/DDR4/LPDDR3/4 memory control數位電路設計。 應徵條件： 1. 碩士以上。 2. 具1年以上 DDR memory control開發相關經驗者為佳。電機工程學類,電子工程學類,通信學類

工作項目： 1. Physical design and implementation from netlist to GDS out. 2. Design signoff including timing closure and physical verification. 3. Physical design methodology development and enhancement. 應徵條件： 1. 碩士以上; 電機工程、電信工程、電控工程、電子工程、資訊工程、資訊科學等相關科系畢業為主。 2. 具5年以上下列相關經驗者為佳： (1) 熟悉相關 EDA tools(Innovus, ICC, ICC2)。 (2) 熟悉 IC後段設計流程，具相關 APR經驗實際參與並執行 project與 tape-out者。 (3) 對於開發及推廣 Physical Design Flow有興趣者。 (4) 具程式設計(TCL,Perl,Python)能力者為佳。電機工程學類,電子工程學類,資訊工程學類

工作項目： 1. Responsible for ASIC Backend / Physical Implementation, including floorplan, power plan, physical synthesis, clock tree synthesis, routing, si, DFM, DRC/LVS in both hierarchical and low power designs. 2. Responsible for Physical Design flow research, development and automation. 工作地點：南部科學工業園區-台南園區 應徵條件： 1. 大學以上電機資訊相關科系畢 2. 熟悉 IC 後段設計流程, 具相關 APR 經驗者佳. 3. 對於開發及推廣 Physical Design Flow 有興趣者. 4. 熟悉相關 tools(Astro, Encounter, IC Compiler)者尤佳 5. 具程式設計(TCL,Perl,C/C++)能力者佳。電機工程學類,電子工程學類,資訊工程學類

(1) 碩士以上電機、資訊相關科系畢業。 (2) 熟悉 Verilog RTL、Synthesis、Simulation、Timing Analysis 等相關 IC Design Flow。 (3) 熟悉 Design for Testability 技術，包含 Scan / ATPG、Delay Test、Memory BIST、Boundary Scan、Diagnosis 等。 (4) 有 DFT Tools (如 DFT Compiler、TetraMAX、BSD Compiler、FastScan、TestKompress、MBISTArchitect) 使用經驗者佳。 (5) 積極負責、勇於迎接挑戰，對於 Nanometer / SoC DFT Implementation、開發及推廣設計流程有興趣者。電機工程學類,電子工程學類,資訊工程學類

1. 數位電路設計、模擬與驗證 2. AMBA(AHB/APB)與IP整合 3.微控制器、微處理器架構設計 4.Audio/Speech相關演算法開發與設計 5.協助開發與驗證FPGA電路 6.RTL Synthesis , Design Timing Constraint 7.POR、BOR、LVR、IO PAD、PWM、Level-shifter、SRAM、ADPLL設計(SPICE simulation)電機工程學類,電子工程學類,資訊工程學類