274

1. 新產品開發驗證、除錯及測試。 2. 電子電路設計及韌體程式設計。 3. 跨部門合作、鑑定、確認及解決相關研發的問題。 [如具相關工作經驗, 薪資另議]電機工程學類,電子工程學類,光電工程學類

應徵人數|1-5 人

2024/03/29

1. IC設計流程自動化開發與維護 2. EDA軟體/IP安裝與管理 3. 評估EDA軟體及矽智財 (Silicon IP) 需求 4. 協助提供學界EDA軟體及矽智財使用服務並提供技術支援 5. 其他主管交辦事項電機工程學類,資訊工程學類,電子工程學類

應徵人數|1-5 人

2024/03/29

1.Embedded Linux development experience. 2.Linux Camera device driver experience. 3.Understood video input(MIPI/LVDS) and video output(HDMI/MIPI/LVDS) and image process(mixer/overlap…..) 4.Understood UVC/IP Camera and exprience. 5.Understood Multimedia API includes GStreamer/V4L2/DirectShow. 6.加分: Qualcomm/MTK/NXP… SoC experience.資訊工程學類,電機工程學類,電子工程學類

應徵人數|1-5 人

2024/03/29

1. 系統設計與整合組裝 2. 電子電路設計、試作與測試評估 3. 協助電路系統檢修、組裝與測試 4. 主管交辦事項電機工程學類,電子工程學類,資訊工程學類

應徵人數|1-5 人

2024/03/29

1.在Linux平台上,使用C/C++和Java/Javascript語言,實現Smart TV/smart monitor的應用層功能開發。 2.協助第三方模組化軟體的移植,讓我們的產品更具擴展性和可靠性。 3.參與新的智慧型電視功能和OTT應用程式的開發,並為客戶提供客製化方案。 4.使用Java/Javascript語言,進行程式碼整合,確保產品的各個模塊之間穩定運作。 5.利用相關工具(ICE/JTAG等)進行問題的分析和除錯,確保產品的穩定性和可靠性。電機工程學類,電子工程學類,資訊工程學類

應徵人數|1-5 人

2024/03/29

Memory電路設計;TEG電路設計; 『具工作經驗者,薪資另議』電機工程學類,電子工程學類

應徵人數|1-5 人

2024/03/29

1.Embedded Linux development experience. 2.Understood video input(MIPI/LVDS) and video output(HDMI/MIPI/LVDS) and image process(mixer/overlap…..) 3.Understood 3D system architecture. 4.加分: Qualcomm/MTK… SoC experience.資訊工程學類,電機工程學類,電子工程學類

應徵人數|1-5 人

2024/03/29

1.熟悉IC Design flow & skill (FPGA,RTL Coding & Verification, Synthesis, STA, Post-Sim) 2.具備whole-chip整合經驗 3.熟悉IC 整合與驗證流程 4.熟悉SOC或DSP或NPU 架構

應徵人數|1-5 人

2024/03/28

1. IC數位邏輯設計模擬與合成。 2. FPGA的合成規劃與測試驗證。 3. 後端STA/DFT/LEC/Post-Sim。 4. 協助IC的除錯與驗證。資訊工程學類,電機工程學類,電子工程學類

應徵人數|1-5 人

2024/03/28

1.熟悉IC Design flow & skill (FPGA,RTL Coding & Verification, Synthesis, STA, Post-Sim) 2.具備數位IC產品設計經驗者.

應徵人數|1-5 人

2024/03/28

1. 記憶體陣列讀寫電路設計、佈局、驗證、量測等工作; 2. 感測器陣列讀寫電路設計、佈局、驗證、量測等工作; 3. Compute in Memory電路設計、佈局、驗證、量測等工作。 4. 其他主管交辦事項電機工程學類,電子工程學類

應徵人數|1-5 人

2024/03/28

Job function: 1. Work with Digital Design team for Physical Design of SoC chips including top level floor planning, block partition, timing budgeting, power planning, block integration, whole chip timing closure, and tape out. 2. Responsible for physical design methodology research and development. 3. Cross site projects coordination and management. Requirement: 1. MS with 5+ years of experience in Physical Design. 2. Familiar with Unix/Linux environment and scripts. 3. Familiar with ASIC design flow. 4. Familiar with Physical Design EDA tools. 5. Good communication and team working skills. 6. Experience in handling large scale SoC chip implementation is a plus.

應徵人數|1-5 人

2024/03/27

Key qualifications: 1. Master degree or above with EE or CS background 2. Familiar with SystemVerilog and Verilog 3. Exposure to OVM/UVM/VMM methodology 4. Exposure to constrained-random based verification environment 5. Exposure to create coverage model and drive coverage closure in including code/functional coverage. 6. Be able to develop a test bench from scratch Preferred qualifications: 1. Familiar with PCI/USB/SATA/Serdes 2. Familiar with Bluetooth 3. Familiar with SOC bus fabric and AXI/AHB/OCP bus protocols 4. Familiar DDR2/3/4 5. Familiar with any type of flash memory 6. Familiar SVA 7. Familiar Formal verification methodology 8. Experience of writing bootloader for ARM/MIPS CPUs 9. Perl/Python experience Job descriptions: 1. Test plan creation 2. Develop testbench, test cases, reference model, coverage model and regression suite 3. Run RTL and gate level simulation, debug failures, manage bug tracking 4. Drive and achieve coverage closure (MD17C0031)電機工程學類,電子工程學類,資訊工程學類

應徵人數|1-5 人

2024/03/27

工作項目: 負責下列工作項目之一 1. Digital Verification Flow. (1) RTL signoff for Lint/CDC/RDC/Constraint. (2) Formal/Simulation/Equivalence checking. (3) Power analysis/optimization、Low power verification. 2. Digital Implementation Flow. (1) High performance/high congestion core synthesis. (2) Advanced-process nodes STA analysis. 3. Characterization and Signoff Margining Flow. (1) Standard/memory cell characterization and circuit exploration. (2) Timing signoff margining analysis and calibration. 應徵條件: 1. 碩士以上;電機、電機與控制、電信、電子、資工、資訊相關科系畢業為佳。 2. 具備3年以上相關工作經驗為佳。 3. 熟悉 Linux工作環境以及 TCL/Perl/Shell script. 4. 熟悉 Front-end Design Implementation EDA Tool.

應徵人數|1-5 人

2024/03/27

1.Writing behavioral model 2.Responsible for functional verification電機工程學類,電子工程學類,資訊工程學類

應徵人數|1-5 人

2024/03/27

工作項目: Verification for High Speed PHY projects, which includes: 1. Responsibility for test plans, testbench documentation and implementation. 2. Use SystemVerilog language, SVA and UVM methodology for block level verification. 3. Debug tests with design engineers to deliver functionally correct design blocks. 4. Close coverage measures to identify verification holes and show progress towards tape-out. 5. Write scripts to automate routine parts of verification workflow. 應徵條件: 1. 碩士以上; 電子、電機、資工、電信、電控、資科等相關科系畢業為主。 2. 具0~3年下列經驗之一者尤佳: (1) Experience verifying digital logic at RTL using SystemVerilog for FPGAs and/or ASICs. (2) Experience verifying digital systems using standard IP components/interconnects. (3) Experience creating and using verification components and environments in standard verification methodology. 3. Preferred qualifications: (1) Experience with high speed MAC/PHY RTL design or verification. (2) Experience with UVM methodology and coding. (3) Good English verbal communication skills.電機工程學類,電子工程學類,通信學類

應徵人數|1-5 人

2024/03/27

Key qualifications: 1. MS degree or above with EE or CS background 2. Familiar with SystemVerilog and Verilog 3. Exposure to OVM/UVM/VMM methodology 4. Exposure to constrained-random based verification environment 5. Exposure to create coverage model and drive coverage closure in including code/functional coverage. 6. Be able to develop a test bench from scratch Preferred qualifications: 1. Familiar with IEEE 802.3 standard 2. Familiar with TCPIP protocol stacks 3. Familiar Ethernet Switch/Router/NAT 4. Familiar xDSL standards 5. Familiar with 802.11x standards 6. Familiar with SOC bus fabric and AXI/AHB/OCP bus protocols 7. Familiar SVA 8. Familiar Formal verification methodology 9. Perl/Python experience Job descriptions: 1. Test plan creation 2. Develop testbench, test cases, reference model, coverage model and regression suite 3. Run RTL and gate level simulation, debug failures, manage bug tracking 4. Drive and achieve coverage closure (MD17C0031)電機工程學類,電子工程學類,資訊工程學類

應徵人數|1-5 人

2024/03/27

工作項目: Flash controller電路開發 應徵條件: 1. 碩士以上;電機工程、電信工程、資訊工程相關科系畢業為主 2. 具2年以上數位IC設計相關經驗者為佳 (MD1880018)電機工程學類,電子工程學類,資訊工程學類

應徵人數|1-5 人

2024/03/27

工作項目: 負責下列工作之一 1. SoC 平台開發及產品線支援。 2. 微處理器開發。 3. 低功耗軟體平台開發。 應徵條件: 1. 碩士以上;電機、資訊科學、資訊工程、電子相關科系畢業為主。 2. 熟悉 Verilog RTL及Synthesis, Simulation, Verification 等相關 IC Design Flow. 3. 熟悉 Computer Architecture 4. 具下列經驗者尤佳: (1) On-chip Bus, DDR/Flash Memory Controller, PCIE, USB等設計 (2) Embedded system軟體開發 (3) ARM CPU 與 ARM/Imagination GPU 整合 (MD1430014)電機工程學類,電子工程學類,資訊工程學類

應徵人數|1-5 人

2024/03/27

工作項目: 1. 建立IC設計後段驗證流程,並撰寫自動化程式。 2. 建立並維護DRC/LVS/SVS/LVL/ERC/PERC相關檔案及流程。 3. 分析並解決PV相關問題。 應徵條件: 1. 碩士以上;電機、電機與控制、電信、電子、資工、資訊相關科系畢業為佳。 2. 無經驗可;具相關工作經驗者佳。 3. 熟悉 Linux工作環境以及 TCL/shell script. 4. 熟悉 Calibre(含TVF及SVRF)或 ICV. 5. 熟悉 FinFET或 BCD製程為佳。電機工程學類,電子工程學類,通信學類

應徵人數|1-5 人

2024/03/27