Job function: 1. Work with Digital Design team for Physical Design of SoC chips including top level floor planning, block partition, timing budgeting, power planning, block integration, whole chip timing closure, and tape out. 2. Responsible for physical design methodology research and development. 3. Cross site projects coordination and management. Requirement: 1. MS with 5+ years of experience in Physical Design. 2. Familiar with Unix/Linux environment and scripts. 3. Familiar with ASIC design flow. 4. Familiar with Physical Design EDA tools. 5. Good communication and team working skills. 6. Experience in handling large scale SoC chip implementation is a plus.

Key qualifications: 1. Master degree or above with EE or CS background 2. Familiar with SystemVerilog and Verilog 3. Exposure to OVM/UVM/VMM methodology 4. Exposure to constrained-random based verification environment 5. Exposure to create coverage model and drive coverage closure in including code/functional coverage. 6. Be able to develop a test bench from scratch Preferred qualifications: 1. Familiar with PCI/USB/SATA/Serdes 2. Familiar with Bluetooth 3. Familiar with SOC bus fabric and AXI/AHB/OCP bus protocols 4. Familiar DDR2/3/4 5. Familiar with any type of flash memory 6. Familiar SVA 7. Familiar Formal verification methodology 8. Experience of writing bootloader for ARM/MIPS CPUs 9. Perl/Python experience Job descriptions: 1. Test plan creation 2. Develop testbench, test cases, reference model, coverage model and regression suite 3. Run RTL and gate level simulation, debug failures, manage bug tracking 4. Drive and achieve coverage closure (MD17C0031)電機工程學類,電子工程學類,資訊工程學類

工作項目： 負責下列工作項目之一 1. Digital Verification Flow. (1) RTL signoff for Lint/CDC/RDC/Constraint. (2) Formal/Simulation/Equivalence checking. (3) Power analysis/optimization、Low power verification. 2. Digital Implementation Flow. (1) High performance/high congestion core synthesis. (2) Advanced-process nodes STA analysis. 3. Characterization and Signoff Margining Flow. (1) Standard/memory cell characterization and circuit exploration. (2) Timing signoff margining analysis and calibration. 應徵條件： 1. 碩士以上；電機、電機與控制、電信、電子、資工、資訊相關科系畢業為佳。 2. 具備3年以上相關工作經驗為佳。 3. 熟悉 Linux工作環境以及 TCL/Perl/Shell script. 4. 熟悉 Front-end Design Implementation EDA Tool.

1.Writing behavioral model 2.Responsible for functional verification電機工程學類,電子工程學類,資訊工程學類

工作項目： Verification for High Speed PHY projects, which includes: 1. Responsibility for test plans, testbench documentation and implementation. 2. Use SystemVerilog language, SVA and UVM methodology for block level verification. 3. Debug tests with design engineers to deliver functionally correct design blocks. 4. Close coverage measures to identify verification holes and show progress towards tape-out. 5. Write scripts to automate routine parts of verification workflow. 應徵條件： 1. 碩士以上; 電子、電機、資工、電信、電控、資科等相關科系畢業為主。 2. 具0~3年下列經驗之一者尤佳： (1) Experience verifying digital logic at RTL using SystemVerilog for FPGAs and/or ASICs. (2) Experience verifying digital systems using standard IP components/interconnects. (3) Experience creating and using verification components and environments in standard verification methodology. 3. Preferred qualifications: (1) Experience with high speed MAC/PHY RTL design or verification. (2) Experience with UVM methodology and coding. (3) Good English verbal communication skills.電機工程學類,電子工程學類,通信學類

Key qualifications: 1. MS degree or above with EE or CS background 2. Familiar with SystemVerilog and Verilog 3. Exposure to OVM/UVM/VMM methodology 4. Exposure to constrained-random based verification environment 5. Exposure to create coverage model and drive coverage closure in including code/functional coverage. 6. Be able to develop a test bench from scratch Preferred qualifications: 1. Familiar with IEEE 802.3 standard 2. Familiar with TCPIP protocol stacks 3. Familiar Ethernet Switch/Router/NAT 4. Familiar xDSL standards 5. Familiar with 802.11x standards 6. Familiar with SOC bus fabric and AXI/AHB/OCP bus protocols 7. Familiar SVA 8. Familiar Formal verification methodology 9. Perl/Python experience Job descriptions: 1. Test plan creation 2. Develop testbench, test cases, reference model, coverage model and regression suite 3. Run RTL and gate level simulation, debug failures, manage bug tracking 4. Drive and achieve coverage closure (MD17C0031)電機工程學類,電子工程學類,資訊工程學類

工作項目： Flash controller電路開發 應徵條件： 1. 碩士以上;電機工程、電信工程、資訊工程相關科系畢業為主 2. 具2年以上數位IC設計相關經驗者為佳 (MD1880018)電機工程學類,電子工程學類,資訊工程學類

工作項目： 負責下列工作之一 1. SoC 平台開發及產品線支援。 2. 微處理器開發。 3. 低功耗軟體平台開發。 應徵條件： 1. 碩士以上；電機、資訊科學、資訊工程、電子相關科系畢業為主。 2. 熟悉 Verilog RTL及Synthesis, Simulation, Verification 等相關 IC Design Flow. 3. 熟悉 Computer Architecture 4. 具下列經驗者尤佳: (1) On-chip Bus, DDR/Flash Memory Controller, PCIE, USB等設計 (2) Embedded system軟體開發 (3) ARM CPU 與 ARM/Imagination GPU 整合 (MD1430014)電機工程學類,電子工程學類,資訊工程學類

工作項目： 1. 建立IC設計後段驗證流程，並撰寫自動化程式。 2. 建立並維護DRC/LVS/SVS/LVL/ERC/PERC相關檔案及流程。 3. 分析並解決PV相關問題。 應徵條件： 1. 碩士以上；電機、電機與控制、電信、電子、資工、資訊相關科系畢業為佳。 2. 無經驗可；具相關工作經驗者佳。 3. 熟悉 Linux工作環境以及 TCL/shell script. 4. 熟悉 Calibre(含TVF及SVRF)或 ICV. 5. 熟悉 FinFET或 BCD製程為佳。電機工程學類,電子工程學類,通信學類

工作項目： 1. High-Performance CPU/GPU Timing & Power Integrity Signoff 2. High-Performance CPU/GPU Post-Silicon Validation & Debug, Sim-to-Silicon Correlation 3. 協同開發 CPU/GPU Advanced DFT, On-Chip PVT Sensor, Performance Improvement & Power Management 等先進技術 4. 支援產品 SoC Projects，協同執行 High-Performance CPU/GPU 專案開發，導入先進 IP 及技術 應徵條件： 1. 碩士以上；電機、資工、電子相關科系畢業為主。 2. 熟悉 SoC Integration & Design Flow、Frontend/Backend/DFT/Timing/IR Drop/Power Analysis EDA Tools。 3. 有 ARM Cortex-A CPU/Subsystem Design/Integration/PPA Optimization/Sign-off 經驗尤佳。 4. 有 Chip-Level, Package & PCB Power Integrity Optimization 經驗尤佳。 5. 有On-Chip PVT Sensor 開發經驗尤佳。 6. 有Post-Silicon Validation, Debug 及 RMA 分析經驗尤佳。 7. 積極負責、溝通協調能力強、勇於迎接挑戰，對於 High-Performance CPU/GPU Technology 有興趣者。電機工程學類,電子工程學類,資訊工程學類

Key qualifications: 1. MS degree or above with EE or CS background 2. Familiar with SystemVerilog and Verilog 3. Exposure to OVM/UVM/VMM methodology 4. Exposure to constrained-random based verification environment 5. Exposure to create coverage model and drive coverage closure in including code/functional coverage. 6. Be able to develop a test bench from scratch 7. Hands on working experience on unit/block/full-chip level verification 8. Good communication skill 9. Leadership/management experience is a plus. Job descriptions: 1. Plan the verification strategy for SOC projects 2. Hands-on verification task of some of the units 3. Work closely with the design teams. 4. Drive the verification team, problem-solving on day-to-day works 5. Provide the measurable metrics for project leads and upper management. 6. Bug/coverage trend identification. Foresee the possible issues and plan for them. (MD17C0031)電機工程學類,電子工程學類,資訊工程學類

工作項目： 1. CPU & GPU Backend Implementation (APR) 2. CPU/GPU Backend Flow Development, Enhancement & Automation 3. Advanced CPU/GPU Technology Development: High-performance, Low Power, and PPA Optimization 應徵條件： 1. 碩士以上；電機、資工、電子相關科系畢業為主。 2. 熟悉 APR Tools (Innovus、ICC2、Fusion Compiler…)，有Synthesis、STA/IR Analysis、Physical Verification等相關經驗者佳。 3. 具備程式設計能力，熟悉 TCL/Perl/C++/Python。 4. 有 High Performance CPU/GPU APR經驗尤佳。 5. 積極負責、勇於迎接新挑戰，對於 High-Performance CPU/GPU Technology 有興趣者。電機工程學類,電子工程學類,資訊工程學類

工作項目： Design verification, UVM 應徵條件： 1. 大學以上；電機、電機與控制、資訊科學、自動控制、電信、資訊工程、電子、動力機械相關科系畢業為主。 2. 具3~5年design verification 相關經驗者為佳。 (MD1680021)電機工程學類,電子工程學類,通信學類

工作項目： 1. Responsible for ASIC Backend / Physical Implementation, including floorplan, power plan, physical synthesis, clock tree synthesis, routing, si, DFM, DRC/LVS in both hierarchical and low power designs. 2. Responsible for Physical Design flow research, development and automation. 應徵條件： 1. 大學以上電機資訊相關科系畢 2. 熟悉 IC 後段設計流程, 具相關 APR 經驗者佳. 3. 對於開發及推廣 Physical Design Flow 有興趣者. 4. 熟悉相關 tools(Astro, Encounter, IC Compiler)者尤佳 5. 具程式設計(TCL,Perl,C/C++)能力者佳。電機工程學類,電子工程學類,資訊工程學類

工作項目： 1. ARM Architecture based Complex CPU Subsystem Platform Design & Integration, Add-on Features Enablement and IP Development 2. SoC Architecture Exploration, Performance Projection and Bottleneck Analysis 3. Benchmark/Power Characterization on Emulation Platform, Result Analysis and Optimization 4. CPU Architecture/Micro-architecture Research 5. Involvement of Post-silicon Bring-up and Debug 應徵條件： 1.碩士以上；電機、資工、電子相關科系畢業為主。 2.具IP開發經驗，熟悉 SoC Integration & Design Flow、Frontend Timing/Power Analysis EDA Tools。 3.熟悉ARMv7/v8-A CPU 架構及AMBA protocol，有 ARM Cortex-A CPU/Subsystem Design/Integration/PPA Optimization/Sign-off 經驗尤佳。 4.具Emulation platform (Zebu, Palladium)經驗尤佳。 5.有 Low Power Design & Verification、Post-Silicon Validation & Debug 經驗尤佳。 6.積極負責、溝通協調能力強、勇於迎接挑戰，對於 High-Performance CPU Technology 有興趣者。電機工程學類,電子工程學類,資訊工程學類

工作項目： DDR Digital PHY design. 應徵條件： 1. 碩士以上; 電機工程、電信工程、電控工程、電子工程、動力機械、自動控制、通訊工程等相關科系畢業為主。 2. 具4年以上 DDR3/4/5 or LPDDR4/5 PHY設計等相關經驗者尤佳。電機工程學類,電子工程學類,通信學類

工作項目： 5G Ethernet NIC開發，包含前段與後段。 應徵條件： 1. 碩士以上; 電機工程、電信工程、電子工程、通訊工程相關科系畢業為主。 2. 熟悉 Verilog, DCG, VCS, PrimeTime, Spyglass. 3. 具1~4年 IC design相關經驗者為佳。資訊工程學類,電子工程學類,電機工程學類

Job Description： 1. Locate in Seoul, Korea. 2. Provide pre-sales and post-sales support. 3. Understand customer requirements, and deliver technical presentations, reports, documents, and technology demonstrations. 4. Support customer product development and design. 5. Support customer issue analysis and resolution. 6. On-site support for debugging or certification tests. 7. Cross-functional collaboration with Realtek internal resources. Education, Skills, Abilities, And Experience Required： • M.S. or B.S. in Electrical Engineering or equivalent. • Fluent in Korean language verbally and in written. • 3 to 5 years of progressive professional technical experience in IC design or related areas, direct experience in IC design house FAE is preferred. • Strong analytical and problem-solving skills. • Strong written/verbal communication and negotiation skills. • SoC/MCU FW programming skill is a plus • Tool SW utility experience is a plus • Being proactive and willing to take initiative. • Ability to work independently to achieve goals. • Ability to understand and explain technical issues and solutions to technical and non-technical personnel. • Medium or higher English skills. • Familiarity with Ethernet protocols will be a plus. • Familiarity with the Automotive ecosystem will be a plus. • Basic or higher Chinese skills will be a plus. • Experience of Linux will be a plus Industry： Automotive Ethernet, Semiconductor Job Functions： Engineering, Business Development電機工程學類,電子工程學類,通信學類

應徵條件： 1. 瑞昱強力招募(1)113年度研發替代役及(2)預聘113年應屆畢業之碩士、博士生。 2. 碩士以上之電子、電機、電信、電控、資工、資科等相關科系，並具下列任一條件者佳： a. 熟悉數位信號處理、數位通信系統。 b. 熟悉於影像系統或數位影像處理，或影像壓縮/解壓縮演算法。 c. 熟悉計算機架構或對SoC設計有興趣者。 d. 具有電路設計、製程整合、元件經驗或有興趣者。 e. 熟悉HDL設計。 f. 對通訊網路、聯網多媒體、多媒體、電腦週邊、車用電子產品或程式設計有濃厚興趣者。電機工程學類,電子工程學類,通信學類

工作項目： 1.AP/Router SoC & Platform development, Network & Peripheral IP design 應徵條件： 1. 碩士以上；電機、電機與控制、電信、電子相關科系畢業為主 2. 具3年以上數位IC 相關經驗者為佳。 (MD1720006)電機工程學類,電子工程學類,資訊工程學類