1. MOSFET device research and development, especially Trench MOSFET/ SGT/ SJ. a). Define device layout design and product design rule b). TCAD simulations to build device structure c). Device measurement d). DOE plan for MOSFET new product 2. Interface with Product engineer and Marketing. 3. EFA/ PFA for trouble shooting 4. Build related patent for new design材料工程學類,電機工程學類

1.Frame layout design and generation. 2.Tapeout data preparation 3.Optical kerf and test mask layout. 4.Kerf layout library maintain. 『具工作經驗者，薪資另議』電子工程學類,電機工程學類,資訊工程學類

1. New device/platform research and development, especially Transient Voltage Suppressor(TVS), ESD/Surge protection a). TCAD simulations to build process condition and device structure b). Define device layout design and product design rule c). EFA/ PFA for trouble shooting 2. Interface with Product engineer and Marketing 3. Build related patent for new design電機工程學類,材料工程學類

積體電路佈局設計 熟悉 Cadence tools, Hercules DRC/LVS, Calibre DRC/LVS 『具工作經驗者，薪資另議』電機工程學類,電子工程學類,資訊工程學類

1. 電子電路分析及設計。 2. 電路圖及PCB Layout製。 3. 樣品焊接電子工程學類普通重機車

1. Calibre DRC/LVS rule writing. 2. PERL or TCL language programming. 3. SKILL language programming. 4. Virtuoso / Laker editor usage. 5. Be familiar with the mask tape out procedure 『具工作經驗者，薪資另議』電機工程學類,電子工程學類,資訊工程學類

1. Calibre DRC/LVS rule writing. 2. PERL or TCL language programming. 3. SKILL language programming. 4. Virtuoso / Laker editor usage. 5. Be familiar with the mask tape out procedure電機工程學類,電子工程學類

Job function: 1. Work with Digital Design team for Physical Design of SoC chips including top level floor planning, block partition, timing budgeting, power planning, block integration, whole chip timing closure, and tape out. 2. Responsible for physical design methodology research and development. 3. Cross site projects coordination and management. Requirement: 1. MS with 5+ years of experience in Physical Design. 2. Familiar with Unix/Linux environment and scripts. 3. Familiar with ASIC design flow. 4. Familiar with Physical Design EDA tools. 5. Good communication and team working skills. 6. Experience in handling large scale SoC chip implementation is a plus.

工作項目： 1. High-Performance CPU/GPU Timing & Power Integrity Signoff 2. High-Performance CPU/GPU Post-Silicon Validation & Debug, Sim-to-Silicon Correlation 3. 協同開發 CPU/GPU Advanced DFT, On-Chip PVT Sensor, Performance Improvement & Power Management 等先進技術 4. 支援產品 SoC Projects，協同執行 High-Performance CPU/GPU 專案開發，導入先進 IP 及技術 應徵條件： 1. 碩士以上；電機、資工、電子相關科系畢業為主。 2. 熟悉 SoC Integration & Design Flow、Frontend/Backend/DFT/Timing/IR Drop/Power Analysis EDA Tools。 3. 有 ARM Cortex-A CPU/Subsystem Design/Integration/PPA Optimization/Sign-off 經驗尤佳。 4. 有 Chip-Level, Package & PCB Power Integrity Optimization 經驗尤佳。 5. 有On-Chip PVT Sensor 開發經驗尤佳。 6. 有Post-Silicon Validation, Debug 及 RMA 分析經驗尤佳。 7. 積極負責、溝通協調能力強、勇於迎接挑戰，對於 High-Performance CPU/GPU Technology 有興趣者。電機工程學類,電子工程學類,資訊工程學類

工作項目： 1. CPU & GPU Backend Implementation (APR) 2. CPU/GPU Backend Flow Development, Enhancement & Automation 3. Advanced CPU/GPU Technology Development: High-performance, Low Power, and PPA Optimization 應徵條件： 1. 碩士以上；電機、資工、電子相關科系畢業為主。 2. 熟悉 APR Tools (Innovus、ICC2、Fusion Compiler…)，有Synthesis、STA/IR Analysis、Physical Verification等相關經驗者佳。 3. 具備程式設計能力，熟悉 TCL/Perl/C++/Python。 4. 有 High Performance CPU/GPU APR經驗尤佳。 5. 積極負責、勇於迎接新挑戰，對於 High-Performance CPU/GPU Technology 有興趣者。電機工程學類,電子工程學類,資訊工程學類

工作項目： 1. Responsible for ASIC Backend / Physical Implementation, including floorplan, power plan, physical synthesis, clock tree synthesis, routing, si, DFM, DRC/LVS in both hierarchical and low power designs. 2. Responsible for Physical Design flow research, development and automation. 應徵條件： 1. 大學以上電機資訊相關科系畢 2. 熟悉 IC 後段設計流程, 具相關 APR 經驗者佳. 3. 對於開發及推廣 Physical Design Flow 有興趣者. 4. 熟悉相關 tools(Astro, Encounter, IC Compiler)者尤佳 5. 具程式設計(TCL,Perl,C/C++)能力者佳。電機工程學類,電子工程學類,資訊工程學類

電子線路佈線Layout電子工程學類,電機工程學類輕型機車,普通小型車,普通重機車

1協助處理無刷/有刷電路板製程優化 2.協助排除生產狀況異常 3.參與產線優化規劃 4. 參與電控課相關作業及達標準管理 5.歡迎電子相關科系應屆畢業生 6.無經驗可電子工程學類,電機工程學類,機械工程學類

工作項目： 1.Responsible for physical design, including fully custom layout and Auto Placement and Routing. 2.Verification and specification achieved. 應徵條件： 1.大學以上；電機, 電機與控制, 資訊科學, 自動控制, 通訊工程, 電信, 資訊工程, 電子相關科系畢業為主。 2.具相關工作經驗者為佳。 (MD1710005、MD1810021)電機工程學類,電子工程學類,資訊工程學類

工作項目： SoC Physical Design 應徵條件： 1. 碩士以上;電機工程、電子工程、資訊工程相關科系畢業為主。 2. 具0年以上或2至3年相關經驗者為佳。 (MD1840015)電機工程學類,電子工程學類,資訊工程學類

工作項目： 負責 Physical design(APR & IC Fully Layout)。 應徵條件： 1. 碩士以上; 電機、電子、電機與控制、自動控制、計算機、微電子相關科系畢業為主。 2. 對 IC Layout有興趣者為佳，具3-5年以上相關工作經驗者尤佳。電機工程學類,電子工程學類,通信學類

Job function: 1. Work with Digital Design team for Physical Design of SoC chips including top level floor planning, block partition, timing budgeting, power planning, block integration, whole chip timing closure, and tape out. 2. Responsible for physical design methodology research and development. 3. Cross site projects coordination and management. Requirement: 1. MS with 5+ years of experience in Physical Design. 2. Familiar with Unix/Linux environment and scripts. 3. Familiar with ASIC design flow. 4. Familiar with Physical Design EDA tools. 5. Good communication and team working skills. 6. Experience in handling large scale SoC chip implementation is a plus.

工作項目： 1. Physical design and implementation from netlist to GDS out. 2. Design signoff including timing closure and physical verification. 3. Physical design methodology development and enhancement. 應徵條件： 1. 碩士以上; 電機工程、電信工程、電控工程、電子工程、資訊工程、資訊科學等相關科系畢業為主。 2. 具5年以上下列相關經驗者為佳： (1) 熟悉相關 EDA tools(Innovus, ICC, ICC2)。 (2) 熟悉 IC後段設計流程，具相關 APR經驗實際參與並執行 project與 tape-out者。 (3) 對於開發及推廣 Physical Design Flow有興趣者。 (4) 具程式設計(TCL,Perl,Python)能力者為佳。電機工程學類,電子工程學類,資訊工程學類

工作項目：IC layout 應徵條件： 1. 學士以上; 電機工程、電信工程、電子工程、通訊工程等相關科系畢業為主。 2. 具3年以上 IC layout 或相關經驗者為佳。

工作項目： 1. Responsible for ASIC Backend / Physical Implementation, including floorplan, power plan, physical synthesis, clock tree synthesis, routing, si, DFM, DRC/LVS in both hierarchical and low power designs. 2. Responsible for Physical Design flow research, development and automation. 工作地點：南部科學工業園區-台南園區 應徵條件： 1. 大學以上電機資訊相關科系畢 2. 熟悉 IC 後段設計流程, 具相關 APR 經驗者佳. 3. 對於開發及推廣 Physical Design Flow 有興趣者. 4. 熟悉相關 tools(Astro, Encounter, IC Compiler)者尤佳 5. 具程式設計(TCL,Perl,C/C++)能力者佳。電機工程學類,電子工程學類,資訊工程學類