2026校園徵才-研發/製程/製程整合/智慧製造/資訊工程師_竹科/南科

Key qualifications: 

1. MS degree or above with EE or CS background 

2. Familiar with SystemVerilog and Verilog 

3. Exposure to OVM/UVM/VMM methodology 

4. Exposure to constrained-random based verification environment 

5. Exposure to create coverage model and drive coverage closure in including code/functional coverage. 

6. Be able to develop a test bench from scratch 

7. Hands on working experience on unit/block/full-chip level verification 

8. Good communication skill 

9. Leadership/management experience is a plus. 

Job descriptions: 

1. Plan the verification strategy for SOC projects 

2. Hands-on verification task of some of the units 

3. Work closely with the design teams. 

4. Drive the verification team, problem-solving on day-to-day works 

5. Provide the measurable metrics for project leads and upper management. 

6. Bug/coverage trend identification. Foresee the possible issues and plan for them. 

(MD17C0031)

Key qualifications: 

1. Master degree or above with EE or CS background 

2. Familiar with SystemVerilog and Verilog 

3. Exposure to OVM/UVM/VMM methodology 

4. Exposure to constrained-random based verification environment 

5. Exposure to create coverage model and drive coverage closure in including code/functional coverage. 

6. Be able to develop a test bench from scratch 

Preferred qualifications:  

1. Familiar with PCI/USB/SATA/Serdes 

2. Familiar with Bluetooth 

3. Familiar with SOC bus fabric and AXI/AHB/OCP bus protocols 

4. Familiar DDR2/3/4 

5. Familiar with any type of flash memory 

6. Familiar SVA 

7. Familiar Formal verification methodology 

8. Experience of writing bootloader for ARM/MIPS CPUs 

9. Perl/Python experience 

Job descriptions: 

1. Test plan creation 

2. Develop testbench, test cases, reference model, coverage model and regression suite 

3. Run RTL and gate level simulation, debug failures, manage bug tracking 

4. Drive and achieve coverage closure 

(MD17C0031)

工作項目： 

負責下列工作之一 

1. SoC 平台開發及產品線支援。 

2. 微處理器開發。 

3. 低功耗軟體平台開發。 

應徵條件： 

1. 碩士以上；電機、資訊科學、資訊工程、電子相關科系畢業為主。 

2. 熟悉 Verilog RTL及Synthesis, Simulation, Verification 等相關 IC Design Flow. 

3. 熟悉 Computer Architecture 

4. 具下列經驗者尤佳: 

(1) On-chip Bus, DDR/Flash Memory Controller, PCIE, USB等設計 

(2) Embedded system軟體開發 

(3) ARM CPU 與 ARM/Imagination GPU 整合 

(MD1430014)

1.Writing behavioral model 

2.Responsible for functional verification

Joining in specification definition, designing verification platform, developing behavioral models, and responsible for system and functional verification

工作項目： 

DSP/Audio演算法開發、維護及優化。 

應徵條件： 

1. Bachelor‘s degree in EE/CS or similar. 

2. Familiar with coding and optimization skills in C, C++, and assembly. 

3. Experience in DSP SIMD programming. 

4. Preferred Qualifications. 

(1) Experience in embedded system signal processing optimization, any of the following: Tensilica HiFi, CEVA, DSP, … etc. 

(2) Solid understanding and product experienceon on audio signal and audio codec processing and optimization. 

(3) Fundamental machine learning / deep learning knowledge.

工作項目： 

DevOps、CI/CD 軟體開發及維運。 

應徵條件： 

1. Bachelor‘s degree in EE/CS or similar. 

2. Familiar with Linux environment and Python programming language. 

3. Familiar with Gerrit and Jenkins. 

4. Familiar with SDLC, SSDLC, DevOps, DevSecOpts, CI/CD. 

5. Preferred Qualifications: 

(1) Experience in DevOps tool usage, maintain, or management. 

(2) Experience in SQA, SSA. 

(3) Good communication skill and trouble-shooting ability.

Verification for microprocessor designs. Desired skills and experience includes: 

1. Experience in processor design verification: test planning, testbench development, and documentation 

2. Knowledge of assembly language, C/C++ and/or SystemVerilog 

3. Knowledge of SVA or UVM methodology for block and top level verification 

4. Formal property checking/formal verification methodologies 

5. Proficiency in scripting languages such as Python/Perl 

應徵條件： 

1. 碩士以上; 電子、電機、資工、電信、電控、資科等相關科系畢業為主。 

2. 具相關工作經驗者尤佳。

工作項目： 

1. 影像處理。 

2. Machine Learning演算法發展。 

應徵條件： 

1. 碩士以上; 電機工程、電信工程、電控工程、電子工程、資訊工程、資訊科學、動力機械、自動控制、通訊工程相關科系畢業為主。 

2. 熟悉 Machine Learning/DNN model development為佳。

工作項目： 

Compiler、Toolchain 開發、維護及優化。 

應徵條件： 

1. Bachelor‘s degree in EE/CS or similar. 

2. Familiar with Linux environment and Git. 

3. Familiar with C/C++ programming language and MIPS/ARM/RISC-V assembly. 

4. Experience in toolchain development: binutils, GCC, LLVM, newlib, ... etc. 

5. Preferred Qualifications: 

(1) Deep understanding of embedded system development flow. 

(2) Experience in embedded system benchmarking and performance tuning.

大學以上，電機、資訊相關系所畢，具下列任一條件者佳： 

(1)熟C、C++、Assembly、Linux。 

(2)具網路embedded system開發經驗。 

(3)對網路如Ethernet, TCP/IP, NAT, QoS, Network processor/protocols/Architecture有興趣者。 

(4)對網路產品，程式設計有興趣者。

研究所以上，電子、電機、資工、相關科系畢業, 或相關工作3年以上經驗者,具下列任一條件者佳: 

(1) 具有 TV 色彩工程經驗.  

(2) 具有視訊處理相關演算法經驗或濃厚興趣者 

(3) 熟色彩調整校正, 色域轉換等色彩處理經驗者 

(4) 熟 DSP 與影像處理者

DRAM circuits design

1.蝕刻先進製程開發,熟悉實驗流程(實驗、評價解析、方案報告) 

2.協同客戶導入新裝置製程及新技術開發。 

3.維持現有Process Of Record及Trouble-shooting解決問題的能力。 

4.具良好溝通能力,理解客戶需求及跨部門有效溝通。

1. 企業風險管理業務規劃與推動 

2. 協助企業風險標竿學習與管理方法精進研析和推動 

3. 策略風險管理規劃 

4. 整合公司對內風險報告與對外風險資訊揭露 

5. 風險文化建立的推動

工作項目：  

1.負責AFE IP功能與規格驗證，確保設計品質  

2.與團隊討論並定義工程規格，參與產品規格制定流程  

3.進行設計工具之分析、研究與基準測試(Bench Mark Test)，提出優化建議  

4.使用Matlab/Simulink模擬軟體建立PLL/ADC/DAC行為模型的分析  

5.AFE相關的Research, Study and Paper Work  

6.自動化開發與維護  

7.發想並完成發明專利申請，提升技術競爭力 

應徵條件:  

1. 研究所以上電機電子相關系所畢業 

2. 熟PLL/ADC/DAC等電路的特性及驗證 

3. 具Python自動化開發經驗與熟悉車用驗證者尤佳。

研究所以上電機、資訊、應數相關系所畢，有興趣從事觸控晶片韌體設計開發與演算法校調。熟悉C/C++，或熟悉SoC、嵌入式系統架構，具晶片韌體、演算法開發經驗者尤佳。 

工作內容： 

1. Develop and maintain touch firmware. 

2. Develop and tuning touch algorithm. 

3. 依任務需求配合國內外出差。

1.RIE製程 

2.Laser decap 製程 

3.MIP製成 

4.ion milling製程

1.Has electrical failure analysis experience (C-AFM, I-V curve 等測試 

EMMI / InSB / OBIRCH / nano probing等機台操作經驗 

2.Strong analytical and problem-solving skills. 

3.有在 fab / lab / FA-house 尤佳 

4.Equipment installation and maintenance.

新產品/製程導入開發與優化