Senior DV engineer (micro-processor)

Responsible for physical design and development activities of MediaTek’s Ghz ARM/Imagination-based graphics processors, AI processors and neural network DS. 

Involve in activities encompass physical design and analysis of complex and timing-critical graphics processor AI processors and neural network DSP. 

Technical disciplines include Physical Implementation (floor-planning, place and route, RC extraction, timing and power optimization) & signoff (DRC, LVS, STA, PI).

Multi-RAT (6G/5G/4G/3G/2G) modem development. This is a common job description. You may involve at least one or more topics in the following: 

(1) architecture planning 

1.1 Modem/SoC TOP system architecture 

1.2 Modem/SoC CPU system design 

1.3 Modem/SoC DSP system design 

1.4 Modem/SoC BUS system design 

(2) digital circuit design and verification 

2.1 baseband modules 

2.2 digital front-end modules 

2.3 RF/mixed-mode digital control modules 

2.4 Computer/network system modules 

2.5 High speed interface design 

(3) IP integration 

3.1 Clock/reset, test modeand low power mode design 

3.2 floorplan and synthesis development 

(4) Design methodology 

4.1 design flow enhancement (low power/verification/etc) 

4.2 chip MP quality control flow

1. Architecture design and RTL implementation of Smartphone chipset  

2. Smartphone SoC and mobile computing platform 

design.  

3. System bus and mobile peripheral designs  

4. SoC system performance analysis

Wi-Fi架構和數位電路設計 

整個晶片的時鐘、測試和重置規劃 

低功耗數位設計 

從RTL到閘級的SoC晶片整合，包括時序收斂和可測試性 

設計方法和整合流程改進

1. Processor core, cache and peripheral verification 

2. Verification flow and methodology 

3. Advanced tool and verification technology survey

1. Own the top-level integration of internal and third-party IPs into SOC or FPGA platform. 

2. Ensure interface compatibility, clock/reset domain correctness. Resolve integration issues including timing, CDC/RDC, and floorplan. 

3. Work closely with architect to define specification, support physical design team through synthesis constraints and integration guidance, partner with firmware and validation teams to ensure smooth bring-up and validation.

1. 數位 IC 設計 

2. 高速 Ethernet PCS/RSFEC/MAC 設計 

3. 高速電路架構與整合

1. Serdes/High speed interface related PHYD IP architecture planning. 

2. Serdes/High speed interface related PHYD IP RTL coding.  

3. Serdes/High speed interface related PHYD IP front-end and back-end integration.  

4. Co-work with MAC design team and DV team for IP verification.  

5. Co-work with Analog design team for PHY co-simulation.

* 資深SI/PI工程師 

* 封裝/電路板 SI/PI設計與晶片開發於消費型產品, 車用以及企業級高效運算產品 

* 記憶體以及高速Serdes SI/PI設計 

* 高效能CPU/GPU/APU PI以及PDN設計 

* 建立封裝/電路板的高速序號設計準則, PDN電氣規格, 以利產品進行

We are looking for a highly experienced PISI Technical Leader to join our team. The ideal candidate will have extensive experience in Power Integrity and Signal Integrity, with a strong background in high-speed IO interface simulations and PDN analysis. As a PISI Technical Leader, you will guide customers through Signal Integrity and Power Integrity signoff, model and optimize system components, and collaborate with various teams to ensure optimal package, PCB, die, interposer, and substrate designs. 

1. Guide customers to complete Signal Integrity and Power Integrity signoff. 

2. Model and optimize vias, connectors, sockets, breakouts, and various system components using commercial tools. 

3. Perform system-level signal integrity simulation in high-speed IOs such as PCIe, SerDes 

4. Architect and simulate power delivery systems, including multiple dies, substrate, interposer, PCBs, and on-die PDN models. 

5. Collaborate with multiple teams, including layout, design, and customers, to optimize package, PCB, die, interposer, and substrate designs.

The Senior Power Integrity Engineer is responsible for the design and analysis of Power Delivery Networks (PDNs), encompassing voltage regulators, PCBs, substrates, and silicon dies, to drive strategic technology development for data center SoCs. Key responsibilities include conducting power integrity pathfinding, developing both detailed and reduced-order PDN models, and optimizing PDN performance through comprehensive time-domain and frequency-domain analysis. This role requires proficiency in scripting and design automation, as well as expertise in analytical methods and commercial simulation tools (e.g., 2.5D EM solvers) to extract PCB and package impedance profiles and generate accurate N-port models.

The Senior Manufacturing and Test Engineer is responsible for improving manufacturing and test flows to optimize quality, yield and power in AI ASICs. Activities include DFT definition, coverage analysis and test content improvements at socket & system level to drive yield and quality. Collaboration across design and manufacturing teams to correlate pre-silicon to post-silicon through data analysis, building quality models and driving optimizations is expected. Deep understanding and experience in DFT architecture, quality, yield and power measurement flows is needed.

1. Develop and implement DRAM controller/PHY solutions for data-center applications. Validate functionality, improve design to optimize performance, power, latency and efficiency. 

2. Memory controller/PHY Integration: Design and integration memory system.

1. 數位 IC 設計與整合 

2. 執行與管理數位 IC 設計 FE Integration相關任務 

(2.a) RTL level QC，例如 Lint, CDC, RDC 

(2.b) STA timing analysis 與 fixing 

(2.c) synthesis flow 

3. 整合 FE RTL designer 及 BE integrator 團隊合作，針對 PPA（Performance, Power, Area）進行 design 及 clock structure 的優化 

4. 將依應徵者的年資與專業經驗，提供不同的職級

1. 整合IR 資訊和內部團隊合作解決 IR 問題 

2. 產生並分析 power 資訊 

3. 和客戶溝通 IR 相關的 methodology 並開發流程解決問題

1. 數位晶片設計流程與整合  

2. 熟悉低功耗的設計流程(和架構)

1. Familiar to 2.5D or 3D PKG integration & development & mass production experience 

2. From chip architecture view to propose best-fit PKG technology with SIPI, testing, thermal consideration

與晶圓代工廠, 電子設計自動化公司及公司內部團隊合作開發/維護 先進製程/封裝3D/2D設計套件/流程,  

具備單項或多項以下經驗: 

1. 益華電腦或新思科技製程設計套件開發/維護, 及品質檢測 

2. 數位佈局繞線技術檔案開發與維護 

3. 實體驗證規則技術檔案開發如DRC/LVS/PERC/LPE 

4. 有3DIC, CoWoS, Physical Design 或者類比佈局經驗尤佳

1. 應用正規方法在硬體或軟體的驗證上  

2. 正規方法文獻回顧與論文分析以改善目前的使用限制  

3. 規劃安排跨部門的技術教學與討論課程  

4. 相關的文件撰寫與審查修改

根據不同專案使用的各種CPU架構: 

1. 規畫用於system bring-up到量產所需的測試程式 

2. 開發各類功能及SRAM測試程式(程式撰寫與模擬, 機台驗證) 

3. 基於對CPU design的了解以及實驗設計, debug post-silicon DPPM, RMA問題