Embedded Memory IP Designer

1. Serdes/High speed interface related PHYD IP architecture planning. 

2. Serdes/High speed interface related PHYD IP RTL coding.  

3. Serdes/High speed interface related PHYD IP front-end and back-end integration.  

4. Co-work with MAC design team and DV team for IP verification.  

5. Co-work with Analog design team for PHY co-simulation.

• Design, simulate and test various building blocks for photonic ICs such as modulators, filters, and detectors. 

• Develop mathematical models of photonic components for co-simulation with electronic circuits. 

• Contribute to the integration and testing of Photonic & Electronic ICs, collaborate with cross functional teams to improve system performance and optimize designs. 

• Must be proficient in programming (e.g. Python or MATLAB) for design automation

• Chip to Chip 介面類比 PHY 電路，例如 UCIe 標準或客製化的 Die to Die 連結類比電路設計 

• HBM/DDR/LPDDR類比PHY電路設計與混合模式/高速電路設計等。

1. DFT architecture exploration & evaluation for next-gen process node & package technology of MediaTek: 

* Scan chain insertion & ATPG pattern generation 

* Pattern validation through simulation & silicon analysis(pass/fail, shmoo, fail log, etc.) 

* Diagnosis to help manufacture process improvement 

2. Co-work with SoC architect, RTL designer, physical design engineer, and package engineer to define best architecture for 3D-IC: 

* PPA(Performance/Power/Area) impact analysis & mitigation via DFT innovation 

* Develop & integrate DFT-related RTL design modules to test chip

1. 射頻電路系統架構與規格制定 

2. 射頻相關校準與控制演算法開發/驗證. 

1. RFIC architecture and specification design.  

2. RF related calibration algorithm and control flow development/verification. 

3. Communication and DSP system for RF design

(請留意：為加快面試安排時間，2026校招僅限定投遞5個職缺)我們在找這樣的你： 資工/資管/電子/電機/電信/通訊/電控相關研究所背景，對行動通訊、無線及寛頻連結、家庭娛樂晶片解決方案有濃厚興趣的2026年應屆畢業生。 勇於表達意見，以團隊成功為目標，面對困難不輕易放棄，總是在想更好的做法，擁有創新及不斷學習的精神。 聯發科技邀請您，與全球最頂尖的菁英一同合作，彼此激盪最新的創意與解法，共同挑戰每一個不可能。

1. Package related structure stress analysis including warpage, material study.  

2. Package and board level stress modeling for TCT, drop and vibration.  

3. IC and package thermal analysis, modeling and characterization  

4. Chip-Package-PCB thermal co-simulation and design.  

5. System level thermal simulation 6. System level stress simulation

1. Package related structure stress analysis including warpage, material study. 

2. Package and board level stress modeling for TCT, drop and vibration. 

3. IC and package thermal analysis, modeling and characterization 

4. Chip-Package-PCB thermal co-simulation and design. 

5. System level thermal simulation 

6. System level stress simulation

IC 測試開發工程師 

負責高速數位、類比晶片測試程式開發(AP/compu AI/ASIC/…)，產品特性異常分析與改善 

新產品導入量產與生產良率測試時間優化 

俱獨立帶產品作業為佳。

The candidate will design, supervise layout, help characterize transceiver front-end circuits for WiFi and Bluetooth production.

1. Package design and planning of various product.  

2. Design & layout of BGA substrate.  

3. Co-work with package houses for package design 

4. Development of advanced package technology.  

5. Package design platform development.

1. 智慧型手機系統記憶體與儲存: DRAM (LPDDR4, LPDDR5, LPDDR6...) / Storage (UFS, eMMC...)驗証 

2. 系統驗証方法研究與開發 

3. 規畫驗証計畫 (test plan, test case) 

4. 自動化測試環境開發

Analog/Mixed-signal circuit design

28nm及以下先進製程(含FinFET) IO電路和ESD防護設計, 工作內容包含  

(1) GPIO電路設計(包含ESD/LU防護) 

(2) 特殊應用IO (SD3.0/SIM card/eMMC等)電路設計(包含ESD/L防護)  

(3) 高速IO和特殊應用IO在事業部專案上展開和執行 

- Advance node (28nm and beyond, including FetFET) IO circuitry and ESD protection design covering fields for  

(a) General purpose IO circuit design (with ESD/LU protection)  

(b) Specialty IO (SD3.0/SIM card/eMMC etc.) circuit design (with ESD/LU protection)  

(c) Project related implementation for high speed/specialty IO Interface - High speed IO, specialty IO circuit design, ESD protection circuit design and simulation.  

Work with project leader, layout, packaging and system engineers to meet design and system specifications.  

Work with IO library modeling, characterization teams closely for IP release.

1. 平台電源管理系統架構設計與規格定義, 包含功耗/溫度/性能等系統分析. 

2. 系統應用詳細電源需求與控制架構之分析與優化 

3. 電源管理芯片規格制定與新技術之開發.

1. 系統應用電源需求與控制架構分析 

2. 電源管理晶片規格制定與驗證 

3. 類比電路開發與驗證 

4. 驗證電路板設計 

5. 自動化測試開發

Work in Analog/Mixed-Signal Modeling and Verification Methodology Development group to establish, streamline and enhance new and existing AMS Behavioral Modeling related development method, coding and validation process and integration flows, and work hands-on with AMS IP Teams for AMS Behavioral Modeling flow and process experiments, demonstrations, adaptions, and deployment. The candidate will work with AMS IP teams including digital design, analog design, analog behavioral modeling and design verification members, apply and advance existing and evolving AMS Behavioral Modeling methodologies and processes, and contribute to establish and maintain Modeling Platform to ensure High Quality and High Efficiency of Pre-Si AMS Modeling, Validation and Verification delivery towards high quality silicon products. 

• Work in methodology development group to establish, streamline and enhance new and existing AMS Behavioral Modeling related development method, coding and validation process and integration flows. 

• Work with teams to enable deployment of new AMS Behavioral Modeling flow and processes through experiments, demonstrations, adaptions (for real projects in specified areas such as RF, etc) and integration.  

• Document on new flows and processes for AMS Behavioral Modeling. 

• Apply wide range of AMS Behavioral Modeling skills to help and support AMS IP or Chip Teams to establish or enhance new or existing Modeling capabilities, including but not limited to Model Development, Model Validation to ensure Consistency of Behavior with Original Circuit, Integration of Models into various Verification Environment, fixing Modeling issues found in simulation, etc.  

• Contribute to continuous improving on AMS Behavioral Modeling process for better quality and efficiency through methodology and process improvements.  

• Communicate and collaborate with global architecture, design, verification teams to address new needs or requirement on AMS Behavioral Modeling. 

Job Locations: 

• Taiwan:Hsinchu/Taipei 

• India: Bangalore 

• Singapore 

• USA:Santa Clara, CA/San Diego, CA

Work in Analog/Mixed-Signal Design Verification Methodology Development group to establish, streamline and enhance new and existing AMS DV related development method, coding process and integration flows, and work hands-on with AMS IP Teams for AMS DV flow and process experiments, demonstrations, adaptions, and deployment. The candidate will work with digital design, analog design, analog behavioral modeling and design verification teams, apply and advance existing and evolving Digital and AMS Verification methodologies and processes, and contribute to establish and maintain Verification Platform to ensure High Quality and High Efficiency of Pre-Si Verification Delivery towards high quality silicon products.  

• Work in methodology development team to establish, streamline and enhance new and existing AMS DV related development method, coding process and integration flows. 

• Work with teams to enable deployment of new flow and processes through experiments, demonstrations, adaptions (for real projects in specified areas such as SERDES, etc) and integration.  

• Document on new flows and processes for AMS DV. 

• Apply wide range of Digital and/or AMS DV skills to help and support AMS IP or Chip DV Teams to establish or enhance new or existing DV capabilities, including but not limited to developing scalable and portable Test bench, test cases, drivers, checkers, assertions and reference models, and running RTL and Gate Level simulations and reaching all coverage closures.  

• Contribute to continuous improving on AMS DV process for better quality and efficiency through methodology and process improvements.  

• Communicate and collaborate with global architecture, design, verification, and post-Silicon testing teams to address new needs or requirement on DV Support. 

Job Locations: 

• Taiwan:Hsinchu/Taipei 

• India: Bangalore 

• Singapore 

• USA:Santa Clara, CA/San Diego, CA

跨團隊合作(如:數位設計,系統應用, 測試, 製程...)以最佳化系統單晶片/平台競爭力及效能 ‧  

基於類比設計技術背景, 與類比設計團隊合作提供混合信號解決方案或IP, 以最佳化系統單晶片/平台競爭力及效能.  

於計畫開發過程中, 協調類比團隊共同解決相關問題及克服挑戰, 以達成量產目標

高速類比 SerDes 電路設計 

Work Location : 新竹/竹北/台北/台南