數位IC驗證工程師R2

研究所以上電子、電機、資工相關系所組畢。 

職缺需求： 

1. Familiar with Verilog, Perl, synthesis flow and FPGA flow. 

2. Familiar with HW/SW co-simulation flow. 

3. Chip architecture, clock tree planning and low power design.

研究所以上電子、電機、資工相關系所組畢，熟悉或有興趣從事數位訊號處理(DSP)演算法，應用於Touch panel等領域。熟悉C/matlab，熟悉影像處理者尤佳，資深工程師需具三年以上工作經驗。

應徵條件： 

1. 瑞昱強力招募(1)115年度研發替代役及(2)預聘115年應屆畢業之碩士、博士生。 

2. 碩士以上之電子、電機、電信、電控、資工、資科等相關科系，並具下列任一條件者佳： 

a. 熟悉C/C++、硬體描述語言(Verilog)和驗證語言(Vera/systemVerilog)。 

b. 具IC設計經驗者佳。 

c. 對晶片設計驗證或程式設計有濃厚興趣者。

應徵條件： 

1. 瑞昱強力招募(1)115年度研發替代役及(2)預聘115年應屆畢業之碩士、博士生。 

2. 碩士以上之電子、電機、電信、電控、資工、資科等相關科系，並具下列任一條件者佳： 

a. 熟悉數位信號處理、數位通信系統。 

b. 熟悉於影像系統或數位影像處理，或影像壓縮/解壓縮演算法。 

c. 熟悉計算機架構或對SoC設計有興趣者。 

d. 具有電路設計、製程整合、元件經驗或有興趣者。 

e. 熟悉HDL設計。 

f. 對通訊網路、聯網多媒體、多媒體、電腦週邊、智慧互聯、車用電子產品或程式設計有濃厚興趣者。

應徵條件： 

1. 瑞昱強力招募(1)115年度研發替代役及(2)預聘115年應屆畢業之碩士、博士生。 

2. 碩士以上之電子、電機、電信、電控等相關科系，並具下列任一條件者佳： 

a. 熟悉相關tools(Astro, Encounter, IC Compiler)者。 

b. 熟悉IC後段設計流程, 具相關APR經驗及有興趣者。 

c. 對於開發及推廣Physical Design Flow有興趣者。 

d. 具程式設計(TCL,Perl,C/C++)能力者佳。

應徵條件： 

1. 瑞昱強力招募(1)115年度研發替代役及(2)預聘115年應屆畢業之碩士、博士生。 

2. 碩士以上之電子、電機、電信、電控、資工及通信等相關科系，並具下列任一條件者佳： 

a. 熟悉CMOS元件特性。 

b. 熟悉SRAM/其他記憶元件特性。 

c. 熟悉Hspice, Hsim等simulation tool, Virtuso, Laker等layout tool. 

d. 對SRAM/其他記憶體電路設計、測試與生產有興趣者。

應徵條件： 

1. 瑞昱強力招募(1)115年度研發替代役及(2)預聘115年應屆畢業之碩士、博士生。 

2. 碩士以上；電機、資訊等相關科系，並具下列任一條件者佳： 

a. 熟悉Verilog RTL、Synthesis、Simulation、Timing Analysis 等相關 IC Design Flow及有興趣者。 

b. 熟悉 Design for Testability 技術，包含 Scan / ATPG、Delay Test、Memory BIST、Boundary Scan、Diagnosis 等及有興趣者。 

c. 有 DFT Tools (如 DFT Compiler、TetraMAX、BSD Compiler、FastScan、TestKompress、MBISTArchitect) 使用經驗及有興趣者。 

d. 積極負責、勇於迎接挑戰，對於 Nanometer / SoC DFT Implementation、開發及推廣設計流程有興趣者。

工作項目： 

Verification for High Speed PHY projects, which includes: 

1. Responsibility for test plans, testbench documentation and implementation. 

2. Use SystemVerilog language, SVA and UVM methodology for block level verification. 

3. Debug tests with design engineers to deliver functionally correct design blocks. 

4. Close coverage measures to identify verification holes and show progress towards tape-out. 

5. Write scripts to automate routine parts of verification workflow.

徵才條件： 

1. 碩士以上電機資訊相關科系畢 

2. 熟悉 Verilog RTL 及 Synthesis, Simulation 等相關 IC Design Flow 

3. 熟悉 Computer Architecture 

4. 有下列經驗者更佳： 

(1)Microprocessor或DSP相關硬體設計 

(2)On-chip Bus, DDR/Flash Memory Controller, PCIE, USB等設計

Verification for microprocessor designs. Desired skills and experience includes: 

1. Experience in processor design verification: test planning, testbench development, and documentation 

2. Knowledge of assembly language, C/C++ and/or SystemVerilog 

3. Knowledge of SVA or UVM methodology for block and top level verification 

4. Formal property checking/formal verification methodologies 

5. Proficiency in scripting languages such as Python/Perl

Microprocessor design. Desired skills and experience includes: 

1. Knowledge of DSP, microprocessor and computer architecture fundamentals. 

2. Experience in RTL design and ability to make trade-offs between power, performance and area appropriately. 

3. Experience in the microprocessor design cycle: initial concept, micro-architecture, implementation, verification, documentation and support.

工作項目： 

1. Software and utility development for ARM Architecture based Complex CPU Subsystem Platform 

2. CPU function validation and testing software development 

3. CPU post-silicon issue analysis, debug & resolving 

應徵條件： 

1. 碩士以上; 資訊工程、資訊科學、電機工程、電子工程等相關科系畢業。 

2. 熟悉 ARMv7/v8/v9-A CPU 架構，有 ARM Cortex-A CPU system software 經驗尤佳。 

3. 熟悉以下經驗者： 

(a) CPU 之系統程式或工具開發。 

(b) CPU/OS之 debug 及問題分析。 

(c) CPU post-silicon issue analysis, debug & resolving。 

(d) 具備 Verilog RTL 及相關工具軟體開發經驗。 

4. 積極負責、溝通協調能力強、勇於迎接挑戰，對於 High-Performance CPU Technology 有興趣者。

工作項目： 

DDR3/DDR4/LPDDR3/4 memory control數位電路設計。 

應徵條件： 

1. 碩士以上。 

2. 具1年以上 DDR memory control開發相關經驗者為佳。

工作項目： 

10G Server NIC MAC開發與驗證、後段整合，如： 

1. Digital IC design. 

2. Chip Integration. 

3. FPGA verification. 

應徵條件： 

1. 碩士以上; 電機工程、電信工程、電子工程、通訊工程相關科系畢業為主。 

2. 熟悉 Verilog, DCG, VCS, PrimeTime, Spyglass. 

3. 精通英文。 

4. 具相關經驗者為佳。

工作項目： 

1. Finding solutions for creative applications. 

2. RTL coding for function implementation, including simulation. 

3. Discuss function spec with system designer 

4. Architecture planning for circuit design. 

5. Completing front-end design flows, such as synthesis, linting, asynchronous checking, STA and so on. 

應徵條件： 

1. 碩士以上; 電機工程、電信工程、電控工程、電子工程、資訊工程、資訊科學、動力機械、自動控制、通訊工程等相關科系畢業為主。 

2. 經驗不拘，具二年以上相關工作經驗者尤佳。 

3. 對所有視覺相關產品有熱情、有想法。 

4. 熟悉以下 HDL/Tool(愈多項或單項愈熟尤佳)： 

verilog, verdi, LEC, linting, perl, synthesis, static timing analysis, Clock tree architecture. 

5. 對以下領域有了解更佳(不必全部)： 

5.1 Video codec(AVS3, AV2, VP9, HEVC, H.264, and etc.) 

5.2 High speed interface, such as HDMI, DDR, USB, and so on. 

5.3 Image/Video processing. 

5.4 CPU, GPU, and NPU.

工作項目： 

1. SOC integrator! 

A challenging job for integrating the designs from over 100 digital designers and tens of analog designers. 

A challenging job of using deep submicron process. 

2. Building & Improving the standard environment for digital designers to run front-end flow, such as synthesis, STA analysis, linting, and so on. 

3. Cooperating with APR designers for backend timing closure. 

4. Block / Whole-Chip CTS (Clock-tree Synthesis) analysis and improvement. 

應徵條件： 

1. 碩士以上; 電機工程、電信工程、電控工程、電子工程、資訊工程、資訊科學、動力機械、自動控制、通訊工程等相關科系畢業為主。 

2. 熟悉 verilog, verdi, STA, synthesis. 

3. 具 CTS(Clock tree synthesis) Design/Debug經驗者尤佳。 

4. 會寫 script如 perl者更佳。 

5. 具六年以上相關工作經驗。

工作項目： 

1. High-Performance CPU/GPU Timing & Power Integrity Signoff  

2. High-Performance CPU/GPU Post-Silicon Validation & Debug, Sim-to-Silicon Correlation 

3. 協同開發 CPU/GPU Advanced DFT, On-Chip PVT Sensor, Performance Improvement & Power Management 等先進技術 

4. 支援產品 SoC Projects，協同執行 High-Performance CPU/GPU 專案開發，導入先進 IP 及技術 

應徵條件： 

1. 碩士以上；電機、資工、電子相關科系畢業為主。 

2. 熟悉 SoC Integration & Design Flow、Frontend/Backend/DFT/Timing/IR Drop/Power Analysis EDA Tools。 

3. 有 ARM Cortex-A CPU/Subsystem Design/Integration/PPA Optimization/Sign-off 經驗尤佳。 

4. 有 Chip-Level, Package & PCB Power Integrity Optimization 經驗尤佳。 

5. 有On-Chip PVT Sensor 開發經驗尤佳。 

6. 有Post-Silicon Validation, Debug 及 RMA 分析經驗尤佳。 

7. 積極負責、溝通協調能力強、勇於迎接挑戰，對於 High-Performance CPU/GPU Technology 有興趣者。

工作項目： 

1. CPU & GPU Backend Implementation (APR) 

2. CPU/GPU Backend Flow Development, Enhancement & Automation 

3. Advanced CPU/GPU Technology Development: High-performance, Low Power, and PPA Optimization 

應徵條件： 

1. 碩士以上；電機、資工、電子相關科系畢業為主。 

2. 熟悉 APR Tools (Innovus、ICC2、Fusion Compiler…)，有Synthesis、STA/IR Analysis、Physical Verification等相關經驗者佳。 

3. 具備程式設計能力，熟悉 TCL/Perl/C++/Python。 

4. 有 High Performance CPU/GPU APR經驗尤佳。 

5. 個性積極負責、勇於迎接新挑戰，對於 High-Performance CPU/GPU Technology 有興趣者。

工作項目： 

1.High-Performance CPU & GPU & Armv9 & Server-class Compute SubSystem (CSS) Frontend Implementation (including STD cells/SRAM analysis & selection, DFT insertion, Synthesis, low power cells insertion & verification) 

2.Advanced ASIC Implementation Flow Development & Automation: High-performance, Low Power, and PPA (Performance, Power, Area) Optimization  

3.Physical Synthesis and Collaboration with P&R in Timing/Congestion Analysis and PPA Optimization  

4.Perform Power Replay and Power Analysis 

5.Perform Pre-layout/Post-layout Quality Checks (including LEC, CLP, ATPG, GCA, PPA quality) 

應徵條件： 

1.碩士以上；電機、電機與控制、資訊工程、電子相關科系畢業為主。 

2.熟悉 Frontend EDA Tools、Synthesis、Timing Analysis、Low Power Implementation Flow & PPA (Performance, Power, Area) Optimization。 

3.有開發Automation Flow的經驗，熟悉 TCL/Perl/Python。 

4.英文能力良好，聽說讀寫精通。 

5.有 CPU、GPU、Multi-Core Processor、Compute SubSystem Implementation 經驗尤佳，例如 Synthesis/Floorplan/CLP/DFT等。 

6.積極負責、勇於迎接挑戰，對於 High-Performance CPU/GPU/CSS、Advanced PPA Optimization、Energy Efficiency Technology 有興趣者。

應徵條件： 

1. 碩士以上；電機、電機與控制、資訊工程、電子相關科系畢業為主。 

2. 熟悉 Verilog RTL Design、SoC Integration & Design Flow、Frontend EDA Tools、Synthesis & STA Methodology、Low Power Design & Verification。 

3. 具備 IP Integration、Hierarchical Implementation、Verification 能力；熟悉 TCL/Perl/C++/Python。 

4. 英文能力良好，聽說讀寫精通。 

5. 有 CPU、GPU、Multi-Core Processor Development 經驗尤佳，例如 Design/Integration/Synthesis/DFT/Timing Closure/Sign-off/Production 等。 

6. 積極負責、勇於迎接挑戰，對於 High-Performance CPU/GPU、Advanced PPA Optimization、Energy Efficiency Technology 有興趣者。 

工作項目： 

1. High-Performance CPU & GPU Frontend Implementation 

2. Advanced CPU Technology Development: High-performance, Ultra-low Power, and PPA Optimization 

3. Processor Frontend Development Flow Enhancement & Automation 

應徵條件： 

1. 碩士以上；電機、電機與控制、資訊工程、電子相關科系畢業為主。 

2. 熟悉 Verilog RTL Design、SoC Integration & Design Flow、Frontend EDA Tools、Synthesis & STA Methodology、Low Power Design & Verification。 

3. 具備 IP Integration、Hierarchical Implementation、Verification 能力；熟悉 TCL/Perl/C++/Python。 

4. 英文能力良好，聽說讀寫精通。 

5. 有 CPU、GPU、Multi-Core Processor Development 經驗尤佳，例如 Design/Integration/Synthesis/DFT/Timing Closure/Sign-off/Production 等。 

6. 積極負責、勇於迎接挑戰，對於 High-Performance CPU/GPU、Advanced PPA Optimization、Energy Efficiency Technology 有興趣者。