職缺描述
1.PCB stack-up design & Constraint Rule setting. 2.Provide SI/PI design suggestions for PCB layout. 3.Signal integrity analysis of high-speed and low-speed signal interfaces. 4.Power integrity design includes DC impedance, AC resonance and capacitance optimization. 5.In addition to Cadence 2.5D EM solution as a daily necessary software, AMD SeaSim/S2Eye, Intel ICAT/IMLC/CCT are also required. 6.Use TCL and Python to shorten the complicated software operation process, generate reports and perform DOE analysis. 7.Familiar with PCB test coupon TDR/TDT measurement and Delta L 4.0 Measurement.
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