全職
碩士
面議(經常性薪資達 4 萬元或以上)
1.SoC Chip Top and Infrastructure integration and physical design
2.Participate in SoC design implementation from logic synthesis to physical implementation stage under the latest technology process
3.Participate in SOC/Sub-System design architecture planning, RTL design rule check, Synthesis, DFT/ATPG, LEC, Timing sign-off, Timing ECO
更多說明:
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