找工作

職責要求 - RTL/Logic Integration and Verification - Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for the blocks and the top level including SOC. - Use cdc tool to check RTL/SDC quality - Hands-on experience on post-silicon debug 任職資格 - Knowledge and design experience of digital flows & FPGA validations - One of the Key Serdes protocol (PCIe, SATA, USB, VBO, MIPI etc.) - Knowledge and design experience of PCS

The candidate will design, supervise layout, help characterize transceiver front-end circuits for WiFi and Bluetooth production.

1. Design and RTL implementation of SoC debug modules 2. Integration and verification of debug components (e.g., trace, monitor, access port) 3. Debug signal capture, trace, and analysis for SoC platforms 4. Support SoC debug flow and issue localization 5. Collaborate with cross-functional teams to optimize debug performance 6. Documentation and test specification for SoC debug features 7. Location: Taipei/Hsinchu

1. 各種產品的封裝佈局圖面繪製及客製化治工具設計 2. 確保產品符合設計規範、品質標準與客戶需求 3. 建立檢測/驗證封裝的標準與流程 4. 建立與維護設計平台及相關資料庫 5. 新技術前期的模擬評估及3D模型建立 6. 跨部門團隊合作，推動新產品開發與導入

工作項目：IC layout 應徵條件： 1. 學士以上; 電機工程、電信工程、電子工程、通訊工程等相關科系畢業為主。 2. 具3年以上 IC layout 或相關經驗者為佳。

IC post Si activities coordination 1) Project post tape out schedule and production cost management 2

1.Full customer IC layout. 2.DRC, LVS verification debug.. 3.Whole chip integration & tapeout flow.

1.數位電路設計 2.多媒體架構與電路設計 3.多媒體系統整合 1.Digital IC Design 2.Multimedia Architecture and Design 3.Multimedia

工作項目： 負責 Physical design(APR 電機、電子、電機與控制、自動控制、計算機、微電子相關科系畢業為主。