找工作

Responsible for digital design verification of power management IC 1. Define verification plan 2. Create testbench and verify design functionality 3. Develop verification environment 4. Explore DV methodology

生醫訊號感測類比電路設計, 系統設計及驗證

對於Smartphone AP SoC，從系統效能、功率消耗、實現與應用成本等多重面向分析產品競爭力，進而從系統角度優化硬體架構及軟體配套策略。

類比/混合信號CMOS電路設計

• Leading Bluetooth protocol stack software development • Leading customer requirement implement and support

從系統效能，功率消耗，溫度控制...等多重面向分析產品競爭力，進而從系統角度優化硬體架構及軟體控制策略。 Optimize hardware architecture and software control strategy in aspects of system performance/power/thermal to improve MediaTek‘s product competitiveness.

Multi-RAT (6G/5G/4G/3G/2G) modem development. This is a common job description. You may involve at least one or more topics in the following: (1) architecture planning 1.1 Modem/SoC TOP system architecture 1.2 Modem/SoC CPU system design 1.3 Modem/SoC DSP system design 1.4 Modem/SoC BUS system design (2) digital circuit design and verification 2.1 baseband modules 2.2 digital front-end modules 2.3 RF/mixed-mode digital control modules 2.4 Computer/network system modules 2.5 High speed interface design (3) IP integration 3.1 Clock/reset, test modeand low power mode design 3.2 floorplan and synthesis development (4) Design methodology 4.1 design flow enhancement (low power/verification/etc) 4.2 chip MP quality control flow

1. 記憶體電路設計與驗證 2. 記憶體編譯器平台開發

Power management IC design Audio IC design Data converter IC design high speed serdes IC design

1.從系統應用功秏分析, 與 IP, SoC 與軟體團隊合作, 推進 SoC low power 軟硬體架構的演進. 2.產品規格定義時, 分析不同架構與 IP 選項, 在系統應用功秏體驗的差異, 產出產品應用 power dash board, 提供產品規格決策的依據. 3.執行或協助功秏量測, 與power model預估的功秏做校正 4.分析PMIC/Power rail 設計, SoC power state 與 data-path power等, 並且提出SOC 設計優化方案 5.提出系統優化的方向, 達到最佳的產品電池使用續航時間與使用體驗