已選條件 1 清空條件
Senior Media Health Engineering Lead, DEG PE[R&D研發]
應徵人數:1-5人
通勤費:來回約 56 元/日

As a Senior Media Health (MH) Product Engineering Lead at Micron, you will be leading a small technical team of a forward-thinking engineers that solves complex problems, responsible for enabling Micron’s products with flawless and issue free release to both internal and external customers. Media Health Product Engineers are the key interface between Research and Development, Test Manufacturing, Marketing, and Quality Assurance departments. As a Media Health Product Engineer, you will work with Product Development Team Leads, Design, and Test Engineering to champion MH and Micron Test flow philosophy. You will have expert capability on the test manufacturing code and testing techniques used to validate and ensure device performance in order to drive guidance. This expertise should include debugging code and product issues aiding other specialists in the characterization of applicable part types. In this role, your additional responsibilities include an in-depth understanding of the details of general device functionality specific to semiconductor memory products, as well as understanding schematics and signal integrity. This job entails working with an established group of highly hardworking engineers looking for collaboration and mentorship on their technical roles. Your Key Responsibilities Will Include Lead a technical team in MH with focus in front end or back end testing Work with Test Manufacturing to provide test guidance to improve product quality, yield, test time along with outlining plans and priorities. Provide ideas for new MH and Architectures to support enhanced test capability to add in future quality, yield, and test efficiency. Debugging and identifying root causes for failures using data, electrical and physical analysis techniques. Also using these techniques to modify existing testing strategies to improve quality and maximize yield and minimize test time. Facilitate test time improvements through flow and pattern optimization. Own the team in finding solutions for an array of different technical challenges that arise.電機工程學類,電子工程學類,資訊工程學類

2022/08/17
應徵人數:1-5人
來回約 56 元/日
2022/08/17
DLA ASIC Design Engineer
應徵人數:1-5人
通勤費:來回約 56 元/日

- To support the AMS activities including development of a DLA (deep-learning-accelerator) ASIC composed of IP including our custom deep-learning engine, PCIe and DDR interfaces, a NOC, cache and CPU complex. - Candidates should have experience in taking designs from architecture specifications, through design, detailed documentation, design verification, physical design, tape-out and silicon validation. While primarily responsible for design, the design engineer must with verification engineers to develop test plans and metrics. Since our designs are high-speed and power/area sensitive, then designer must interact closely with both architects and physical design teams to ensure reaching PPA goals in the target development schedule. - Specific experience with PCIe, DDR and CPU sub-system design is desirable. Experience in the design-integration flow (Lint and CDC audits, SDC generation, UPF generation, synthesis, static-timing, power analysis) is required. - The ideal candidate should have at least 5 - 10 years’ experience in a similar role and MS degree.

2022/08/17
應徵人數:1-5人
來回約 56 元/日
2022/08/17
DRAM Design Validation Engineer[R&D研發]
應徵人數:1-5人
通勤費:來回約 56 元/日

Key responsibilities: We develop design validation plans across several teams including Design, Verification, Validation and Systems. Partnering with design, we develop and perform pre-silicon simulations used to improve our product development timelines. After new parts arrive, we implement the post silicon plans. Collaborating with design and validation teams, we resolve silicon findings and implement design fixes. Partnering with Quality Assurance (QA) Team, we develop or identify new tests to ensure a quality product for our customers. We serve as the product-specific point of contact for several multi-functional teams From time to time there will be opportunities to travel to our other engineering sites across the world. Preferred Skills: We are looking for familiarity with the DRAM and CMOS logic circuit function. Someone who is seen as strong mentor and teammate by fellow coworkers. Demonstrated problem solving skills cross multi-functional groups, both within and outside the department. Excellent problem solving and analytical skills in debugging circuit issues to root cause. Education & Experience Necessary for Success: A Bachelor’s or Master‘s Degree in Electrical or Computer Engineering is ideal for a Product Engineer. We are considering those new to Design or Product Engineering to those with a high level of experience.電機工程學類,電子工程學類,資訊工程學類

2022/08/17
應徵人數:1-5人
來回約 56 元/日
2022/08/17
DRAM Product Engineer - DEG Analytics [DRAM數據分析工程師][R&D研發]
應徵人數:1-5人
通勤費:來回約 56 元/日

As a Product Engineer in the DRAM Engineering Group (DEG) Analytics team, you will be responsible for supporting the team’s mission of developing robust analysis tools, methods, and metrics with wide scale communication to help simplify, automate, and clarify the decision processes in all of DEG. DEG Analytics supports DEG teams including Product, Design-for-Test, Validation and more, in pursuit of company-wide goals of quality and yield improvements, and time-to-market and cost reductions. This team serves all DRAM and Emerging technologies, including DRAM in Sustaining Mode and Development Chips. Responsibilities include, but not limited to: Designing, developing, deploying and maintaining new tools to support DEG teams in data extraction, analysis, visualization, alerts and reporting needs. Maintaining existing tools with user-training and support, debug, and new feature development. Serving as a DEG-wide point-of-contact for Micron data systems and infrastructure. Provide documentation, training and ad-hoc support for data and analysis tools to DEG users. Assisting teams to quickly assess inventory, yield, quality, reliability and product capability performance-to-plan and turn those into forward looking forecasts. Supporting custom data extraction needs of our Technology & Product Group (TPG) Data Science partners. Maintaining a working knowledge of Micron products and customer platforms. Designing and developing new tools and metrics/KPI’s for helping to establish our leadership and innovation in the industry. Working independently towards pre-defined goals and proactively making engineering decisions on your own.電機工程學類,電子工程學類,資訊工程學類

2022/08/17
應徵人數:1-5人
來回約 56 元/日
2022/08/17
SoC Test Design Engineer
應徵人數:1-5人
通勤費:來回約 56 元/日

Responsibilities include, but not limited to: The Design Engineer in the ASIC Development Engineering Group at Micron Technology, Inc., will be core technical individual contributor in design and validation of the CXL product controller. In this highly visible and challenging role, your responsibilities will include architecture development and product definition, system integration and full-chip and block-level validation plan and execution, RTL design and implementation of the controller hardware, synthesis, APR and full timing closure. You will be working very closely with design, firmware, verification, and validation teams both domestic and overseas on different projects. SoC Test Design Engineer is responsible for the design to integrate hardware Design-For-Test (DFT) functionalities, that includes boundaryscan, scan-based logic test, memory test, and high-speed interface testing. Minimum Qualifications: · Knowledge of Digital ASIC Design methodology is required. · Solid knowledge and experience in Verilog language is required. · Hands-on experience with Design CAD tools such as ncsim, Spyglass Lint and CDC, etc. · Good English written and verbal communication skills · Knowledge or experience in SoC test and DFT is a plus · Knowledge of TCL, PERL or Python is a plus. · MS degree in Electrical Engineering (or related fields) with 2+ years of experience or BS + 4 years of experience. Preferred Skills: · Design experience of 2-6 years is desirable. · Ability to establish and maintain good relationships with colleagues · Self-motivated, self-directed, and a team player (on the same team and outside of the team).工程學門

2022/08/17
應徵人數:1-5人
來回約 56 元/日
2022/08/17
Reliability Lead/Manager, DEGTTechnology [R&D研發]
應徵人數:1-5人
通勤費:來回約 56 元/日

What you Will Be Doing As the leader of the DRAM Technology NE(NODE ENABLEMENT) Reliability team, you will manage and develop a team of skilled engineers to be responsible for product reliability assessment by understanding reliability mechanisms, circuit functionality and process/CMOS specifics. Reliability risk assessments will be accomplished through innovation and by engaging cross functionally with partner groups; Design, Technology Development, Product Engineering and Quality teams. As a NE REL leader, you will promote a culture of innovation, growth, and development of REL team and help develop scalable solutions for similar near-memory solutions. Your Key Responsibilities Will Include Manage and develop a team of engineers Adapt and implement Best Known Method Reliability strategies Understand and Identify reliability mechanisms which impact on long term product reliability Define and develop product reliability stresses to enable new process node startup, qualification, yield, and ramp Utilize state-of-art in house engineering equipment to support product rel characterization and electrical failure analysis Utilize statistical tools for detailed data analysis on product to drive reliability assessment Present on technical direction recommendations regularly to teams for reliability mitigation Perform reliability risk assessment at all decision points within the qualification cycle Feedback on product reliability issues by collaborating with internal product engineering groups; Design, Technology Development, and Quality teams電機工程學類,電子工程學類,資訊工程學類

2022/08/17
應徵人數:1-5人
來回約 56 元/日
2022/08/17
Design Verification Engineer
應徵人數:1-5人
通勤費:來回約 56 元/日

As a Design Verification Engineer within the ASIC CXL Development at Micron, you will be responsible for defining efficient and coverage-driven testbench for high-quality design delivery. Job Responsibilities: Verification plan definition, DV environment development in SV/UVM and SV/C Design verification at RTL/Gate level, DV Coverage analysis, Coverage improvement at block and Chip level. Support of assertion and coverage-driven methodology Develop test cases in C/C++ to verify functional operation of that the system level Power and Performance analysis Design verification methodology enhancements Requirements: - BSEE, MSEE, or related fields - More than 3 years ASIC design and verification experience - Experience in PCIe, NVMe, and CXL protocols and storage industry is a plus - In depth knowledge on verification methodology and flow - Familiar with UVM, System Verilog, scripting, and DV tools工程學門

2022/08/17
應徵人數:1-5人
來回約 56 元/日
2022/08/17
SoC platform架構設計工程師
瑞昱半導體股份有限公司
新竹市東區
面議(經常性薪資4萬/月含以上)
應徵人數:1-5人
通勤費:來回約 56 元/日

工作項目: 1. SoC bus architecture 架構設計。 2. 平台效能分析與改善。 應徵條件: 1. 碩士以上; 電機工程、電信工程、電控工程、電子工程、資訊工程、資訊科學、動力機械、自動控制、通訊工程等相關科系畢業為主。 2. 具2年以上 SoC系統架構設計, 或有 DDR controller設計相關經驗者為佳。電子工程學類,電機工程學類,資訊工程學類

2022/08/17
應徵人數:1-5人
來回約 56 元/日
2022/08/17
111年第55次專案人力電子系統研究所13
應徵人數:1-5人
通勤費:來回約 56 元/日

錄取後依考生學經歷、專長、個人特質賦予以下或多項工作: 1.印刷電路板佈局。 2.印刷電路板特性阻抗設計。 3.印刷電路板底片修改與檢查。 4.線路圖繪製與修改。 5.電子電路焊接、佈線及組裝。 6.類比、數位電子電路測試。 7.模組測試輔助裝置設計製作 8.系統裝備及電子電路製作、組裝、測試、除錯及維護。 9.執行線束佈線施工、訊號量測。 10.纜線(例如電源線或網路線等)製作。 11.天線/射頻模組組裝及測試。 12.可配合出差支援各項演訓任務支援。電子工程學類,電機工程學類,資訊工程學類

2022/08/17
應徵人數:1-5人
來回約 56 元/日
2022/08/17
Physical Design Engineer(Foxconn新竹)
應徵人數:1-5人
通勤費:來回約 56 元/日

需要英文視訊面試 · Must have 4+ years of relevant experience with exposure to 10nm or lower nodes. · Ability to independently handle complex blocks to closure right from Synthesis, Worked on at least 2 end to end projects those spanned across entire life cycle of development, Ability to communicate with architecture, RTL design and other remote teams · Performing a wide range of back-end activities, including synthesis of RTL, DFT insertion, power optimization, Floor-planning, PnR (Place and Route), Clock Tree Synthesis (CTS), Timing closure (STA), DRC, LVS, Antenna checks, IR drop (RedHawk), multi voltage checks etc. · Experience of UPF low power design through synthesis, place and route. Must have experience in handling multi power domain designs. · Expertise in Synopsys/Cadence toolset for RTL2GDS execution. · Strong communication skills required. · Candidate should be good with Synopsys tool Primetime Knowledge of STA Aware of Physical design flow and convergence methodologies. · Ability to code scripts in Perl and TCL. · Should also be able to reconcile FV/CLP/PV errors and make corrections to the db for the same.電機工程學類,電子工程學類,資訊工程學類

2022/08/17
應徵人數:1-5人
來回約 56 元/日
2022/08/17
元件設計資深工程師_功率半導體產品(桃二)
台達電子工業股份有限公司
桃園市中壢區
面議(經常性薪資4萬/月含以上)
應徵人數:1-5人
通勤費:來回約 56 元/日

1.半導體元件設計製作 2.半導體元件測試與特性分析 3.半導體材料良率分析 4.半導體材料穩定度與客靠度驗證分析 5.半導體測試程式開發 6.半導體產業市場分析電子工程學類,電機工程學類,光電工程學類

2022/08/17
應徵人數:1-5人
來回約 56 元/日
2022/08/17
數位IC設計工程師
宏正自動科技股份有限公司
新北市汐止區
面議(經常性薪資4萬/月含以上)
應徵人數:1-5人
通勤費:來回約 56 元/日

As a IC Design Engineer, you will design, implement and verify products that use FPGAs and/or ASICs. 1. Participate in the micro architecture and design partition within the FPGAs and/or ASICs and implement design blocks using Verilog. 2. Participate in all phases of FPGA/ASIC design Flow (Synthesis, Place & Route, and Timing Closure). 3. Work with SW/HW team members to bring-up and validate FPGAs and/or ASICs.電機工程學類,電子工程學類

2022/08/17
應徵人數:1-5人
來回約 56 元/日
2022/08/17
台灣半導體研究中心-微機電設計工程師(專案佐理工程師含以上)(計畫人員)_晶片實作組(111-014)
財團法人國家實驗研究院
新竹市東區
面議(經常性薪資4萬/月含以上)
應徵人數:1-5人
通勤費:來回約 56 元/日

1.協助MEMS微機電整合型感測器設計模擬、佈局量測驗證,有CMOS MEMS設計與下線經驗者佳。 2.協助微機電實驗室統計業務。電子工程學類,電機工程學類,機械工程學類

2022/08/17
應徵人數:1-5人
來回約 56 元/日
2022/08/17
驗證分析工程師
應徵人數:1-5人
通勤費:來回約 56 元/日

1. 新產品開發驗證、除錯及測試。 2. 電子電路設計及韌體程式設計。 3. 跨部門合作、鑑定、確認及解決相關研發的問題。 [如具相關工作經驗, 薪資另議]電機工程學類,電子工程學類,光電工程學類

2022/08/17
應徵人數:1-5人
來回約 56 元/日
2022/08/17
DRAM 電路設計工程師
南亞科技股份有限公司
新北市泰山區
面議(經常性薪資4萬/月含以上)
應徵人數:1-5人
通勤費:來回約 56 元/日

1. DRAM circuits design/Simulation 『具工作經驗者,薪資另議』工程學門

2022/08/17
應徵人數:1-5人
來回約 56 元/日
2022/08/17
ASIC Design Engineer/Manager(USB)
香港商默升科技有限公司台灣分公司
新竹縣竹北市
面議(經常性薪資4萬/月含以上)
應徵人數:1-5人
通勤費:來回約 56 元/日

- Good understanding of SoC, architectures, methodologies and related tools. - Good understanding of microprocessors, and computer system architecture. - Good understanding of IPs, integration and verification. - Good programming in Perl, TCL and Shell programming. - Familiar with Ethernet, USB, MCU(ARM core), I2C, MDIO, usage and protocols. - Enjoy challenging work and a Self-motivated and good team player. - Familiar with USB 3.1/3.2/4.0 in protocol is a plus電算機學門,資訊科學學門

2022/08/17
應徵人數:1-5人
來回約 56 元/日
2022/08/17
Design Verification Engineer/Manager (UVM)
香港商默升科技有限公司台灣分公司
新竹縣竹北市
面議(經常性薪資4萬/月含以上)
應徵人數:1-5人
通勤費:來回約 56 元/日

- Knowledge of System Verilog, digital simulation and debug. - Exposure to UVM is desired. - Familiar with USB design is a plus.電算機學門,資訊科學學門

2022/08/17
應徵人數:1-5人
來回約 56 元/日
2022/08/17
Probe Card/Load Board應用工程師(平鎮總部)
CHPT_中華精測科技股份有限公司
桃園市平鎮區
面議(經常性薪資4萬/月含以上)
應徵人數:1-5人
通勤費:來回約 56 元/日

1.專案交期管理。 2.依客戶需求,與客戶討論進行電路設計 3.整合溝通安排PCB Layout進行與模擬。 4.BOM表料件申請與料件時程掌控。電機工程學類,電子工程學類TOEIC Bridge普通小型車

2022/08/17
應徵人數:1-5人
來回約 56 元/日
2022/08/17
Probe Card/Load Board應用工程師(新竹)
CHPT_中華精測科技股份有限公司
新竹市東區
面議(經常性薪資4萬/月含以上)
應徵人數:1-5人
通勤費:來回約 56 元/日

1.專案交期管理。 2.依客戶需求,與客戶討論進行電路設計 3.整合溝通安排PCB Layout進行與模擬。 4.BOM表料件申請與料件時程掌控。電機工程學類,電子工程學類TOEIC Bridge普通小型車

2022/08/17
應徵人數:1-5人
來回約 56 元/日
2022/08/17
電路設計工程師
應徵人數:1-5人
通勤費:來回約 56 元/日

Memory電路設計;TEG電路設計; 『具工作經驗者,薪資另議』電機工程學類,電子工程學類

2022/08/17
應徵人數:1-5人
來回約 56 元/日
2022/08/17