執行專案計畫所需之混和訊號電路設計與整合驗證等相關工作，主要任務如下： 

1.數位、類比及射頻電路整合模擬環境驗證 

2.Cryo-CMOS數位、類比及射頻電路整合電路模擬、量測及驗證 

3.了解Cryo-CMOS 控制讀取電路與量子位元架接需求 

4.其他臨時交辦之事項

[本職缺為計畫人力] 

1.AI on Edge系統晶片平台軟體及硬體開發。 

2.AI視覺應用於無人載具之系統晶片軟體及硬體開發。 

3.機電系統整合開發。 

4.主管交辦事項。

你是否厭倦了一成不變的產品開發工作? 對於技術的停滯感到不安? 

創新技術研發中心集結了光學、機構、電力電子、類比、數位、演算法、韌體、熱流…等各領域菁英，持續關注業界新趨勢的脈動並專注於前瞻性核心技術的研究，以促成公司發展具精準、可靠、獨特性的世界級產品。 

在這裡我們常和各領域高手一起腦力激盪，既發揮長才更同時拓展橫向知識，也可透過產學研合作與外部各領域專家密集互動，更可感受到同僚間相互尊重、關心、協助與分享。 

如果你熱愛研發工作，喜歡創新求變，無畏技術研究的挑戰，歡迎一起加入我們的行列。 

具體工作內容如下: 

高頻寬高精度SMU(Source Meter Unit)研究開發_運用高速線性電路、精密量測電路及數位控制平台進行SMU之開發 

1. 線性放大器電路之架構選取與電路設計 

2. 高頻寬高精度量測線路分析與設計 

3. 電路控制迴路分析與模擬

測試系統設計與測試技術開發及系統整合驗證，並協助產線測試系統順利導入量產，以期提高良率與產出率。 

1.客戶需求及資訊澄清。 

2.制訂部門開發策略，完成測試系統設計開發目標。 

3.分析測試資料及改善測試流程，縮短測試時間 提高產出。 

4.規劃制定測試系統及驗證開發平台，符合模組電測需求。 

5.執行測試系統軟硬體整合順利導入NPI。 

6.發展新測試技術，以建立準確之測試開發流程及準則。 

7.彙整分析研發過程中問題，並給予工程人員或客戶建議。 

8.定期搜集、分析測試數據指標，做為測試程式優化的參考。 

6.發展新測試技術，以建立準確之測試開發流程及準則。

MCU相關類比電路設計：RCOSC , Xtal , Bandgap , LDO , OPAMP , DAC , ADC , POR , LVD 等.

Qualifications 

• Strong knowledge of analog CMOS designs and topologies.  

• Experience with high speed digital circuit (e.g., serializer, deserializer, counters, dividers, etc.) design, analysis and verification. 

• Experience in analyzing link jitter budget for high-speed serial links and creating block level requirements. 

• Knowledge of different PLL/CDR architectures. 

• Experience with PLL/CDR design including building blocks (VCO, charge pump, divider, etc. 

• Modeling of CDR and adaptive loops (using C, Matlab or Python, etc.). 

• Knowledge of ESD requirements. 

• MS with 3+ year experience working on high speed SERDES circuits in advanced CMOS process nodes. 

• Experience in designing op-amps, band gaps, differential amplifiers, LDO 

• Architecture experience with transceiver equalizers (TX FIR, RX analog FFE, CTLE, and DFE) – DSP (FFE and DFE) experience is preferred 

• Strong understanding of signal integrity and EM issues, especially related to serdes channel modelling. 

• Experience with mixed-mode simulation of analog and digital blocks, including behavioral modeling of analog circuits, using tools like verilog or verilogA for simulation. 

• Experience with synthesized digital design flows, using RTL descriptions to synthesize verified netlists for physical implementation. 

• Full-custom analog layout techniques and the ability to take a design and do all the layout extract verification and sign-off. 

• Working experience with high speed NRZ and PAM4 Serdes, PLLs, CDR and FEC. 

• In depth knowledge of the IEEE 802.3 and OIF specifications for 25Gbps and 56Gbps Serdes Interfaces. 

• Working knowledge of system level power integrity and budgeting (DC, AC, transient analysis). 

• Experience of IC mass production 

月薪可面議

JD to be carried out include, but not limited to, the following: 

· Block level and sub-block floor-planning 

· Discuss SRAM placement with PD team during block level floor-planning stage 

· Placement optimization for timing and resolve congestion 

· Clock tree synthesis and clock tree optimization for timing 

· Routing and routing optimization for post-route timing and resolving congestion 

· Clean-up DRC error  

· Post-route timing ECO  

· Metal ECO  

· Clean post-route timing violations  

· Generate SPEF files  

English knowledge 

o BS or MS degree, with basic communication skill.  

o Will need to work with global site teams (Bangalore, Singapore).

1. FPGA加速應用系統整合開發與驗證 

2. IP開發/驗證/整合 

3. 產品除錯與分析支援

1. 類比電子電路開發設計 

2. 電力電子電路開發設計 

3. 數位電路與韌體開發設計 

4. 數控自控軟體,硬體電路開發設計 

5. PLC可程式控制 

工作技能： 開發電子電路系統，類比電路設計 

其他條件：　電路繪圖.電路分析模擬.MCU.DSP.硬體描述語言 

擅長工具： MCU、DSP

1.Responsible for Lab Equipment test and management.  

2.Communication with CP testing house engineering issue include setup testing program and data analysis. 

3.Communication with Assembly house engineering issue include setup Wire bonding and testing program. 

4.Responsible for product yield control ,Engineering lot schedule monitor and supports production planning team.

負責類比電路設計。 

專長: 

1.類比電路設計。 

2.熟悉IC Design flow & skill (HSpice Waveview...)。 

3.熟悉OP、LDO、ADC(SAR)、OSC等MCU周邊類比電路設計。 

4.熟悉USB Power Delivery (PD)類比電路尤佳。

研究所以上電子、電機相關所組畢，具類比積體電路基礎，對類比電路設計，如PLL、USB、ADC、DAC有經驗。

- PLL, Hi-Res audio codec AD/DA, PGA, 

- Audio power amplifier: class G headphone amplifier, class-D, LDO etc.. 

- 麥克風pre-amp, low voltage OPA 

- Sensors AFE, SAR-ADC etc..

電子電路製造或設計, 電源電路製造或設計

軟體程式設計、程式語言C / 組合語言、Embedded Linux system開發、VOIP、數位/類比硬體電路設計

1 The person will contribute to the infrastructure, design, implementation and verification of the software in a team whose job is to develop the next generation of model extractor 

2 This work includes drafting technical specifications, design documents, algorithmic descriptions and test plans. 

3 This will be carried out in close collaboration with other teams abroad. 

4 Provide internal technical support to customer‘s request. 

5 We need our engineers to be versatile, creative and be enthusiastic to take new solutions to push technology forward. 

6 Design and develop the algorithms of parallel process, extracting optimizer. 

7 Research and implement the new technologies and new models.

1. Digital design and development using Verilog HDL. 

2. Work closely with sensor and ASIC design team to implement high speed interface IP, Image Signal Processing IP, timing control logic and any logic block related to CMOS Image Sensor. 

3. Responsible for functional verification both on RTL / gate level simulation and system verification on FPGA platform. 

4. Participate in critical IC tapeout process such as synthesis, STA timing analysis and enhancement and area optimization. 

5. Generate and update Design documentation, attend and present in team meeting for design review and status update.

1.Experienced in CIS process integration and semiconductor devices. 

2.Familiar with CIS pixel layout design and characterization data analysis. 

3.Experienced in CIS pixel device simulation and familiar with optical simulation are plus. 

4.Work with fabs(Si/ CF) to improve pixle related performance.

1.＂Chip+PKG+Board＂ modeling & co-simulation for pre-silicon SI/PI/EMC analysis. 

2.Co-work with RD/CAD/SE for chip design-in SI/PI/EMC issue support. 

3.Gbps interface SI/PI co-design and validation, such as HDMI, VBO, eDP, MIPI, etc. 

4.Provide pkg/board-level SI/PI/EMC design guideline or reference design.

IC及System ESD防護設計

1.＂Chip+PKG+Board＂ modeling & co-simulation for pre-silicon SI/PI/EMC analysis. 

2.Co-work with RD/CAD/SE for chip design-in SI/PI/EMC issue support. 

3.Gbps interface SI/PI co-design and validation, such as DDR2/3, LPDDR1/2, HDMI, VBO, eDP, MIPI, etc. 

4.Provide pkg/board-level SI/PI/EMC design guideline or reference design.

1. 觸控IC , TDDI or 指紋辨識 IC 開發經驗 

2. ADC or sensor IP 開發經驗 

3. TFT-LCD or OLED Display driver IC 開發經驗

1.DC-DC switching regulator design 

2.HV LDO / HV OP design 

3.Charge-pump circuit design 

4.LED driver design 

5.Level Shifter

1.SERDES CMOS Circuit Design ( HDMI,DisplayPort, or USB3.0 ). 

2.All Digital PLL Circuit Design.

1. PLL design 

2. High speed receiver design (1.5Gbps/4Gbps/5.4Gbps/8.1Gbps/12Gbps) 

3. High speed transmitter design (1.5Gbps/4Gbps/5.4Gbps/8.1Gbps/12Gbps) 

4. eDP receiver 

5. V-by-One receiver 

6. MIPI D-PHY 

7. HDMI Receiver 

8. HDMI Transmitter 

9. LCD P2P interface Transmitter

電源電路,電子電路設計或製造及維護修理.

1. 半導體製程技術開發值班工程師。 

2. 需配合日夜值班工作 (四班二輪，做二休二)。 

3. 開發、應用新的半導體相關技術。 

4、製程、生產問題分析，檢視原因並找尋解決辦法 

『具工作經驗者，薪資另議』

Goertek is seeking experienced analog/mixed-signal IC design engineer to focus on developing low noise mixed-signal products including analog-to-digital converters and other blocks in Taipei office. 

Job responsibilities include IC design at both the architectural and transistor level, starting from initial specification through design and layout supervision, silicon evaluation and characterization to product release.

DRAM circuits design

1. IC, package and PCB model extraction & co-simulation for pre-silicon SI/PI/EMC analysis. 

2. SI/PI co-simulation flow development. 

3. Co-work with IC designer to define specification and solve the silicon related SI and PI problems. 

4. Co-work with FAE to provide SI/PI/EMC issue analysis support. 

5. Engage with Computer Aided Design (CAD) tool vendors for tool evaluation and support. 

『具工作經驗者，薪資另議』

1. IC設計軟體使用介面自動化程式開發(所指的設計軟體包含益華電腦[Cadence]，新思科技[Synopsys]，明導科技[Mentor] 公司所開發的IC 設計軟體) 

 操作介面開發之程式開發 

 操作流程整合之程式開發 

所需技能 : 程式開發能力( 具Perl /Python/ Cadence Skill/ C-Shell/C 程式語言或有興趣者 ) 

2. IC設計資料驗證程式開發 

 DRC /LVS /RCX 程式開發 

 電路模擬的測試程式開發 

所需技能 : 程式開發能力( 指的是運用IC設計軟體內建指令所設計出的程式開發或有興趣者) 

薪31,000~57000具經驗者另議

記憶體電路設計 

薪31,000~57000具經驗者另議

精密儀器之電子電路製造或設計及維護修理.

1.新產品或新功能的開發專案、支援應用程式設計工作:  

設計FPGA及DSP/CPU/ARM相關週邊電路及工控/通信子板  

設計高速FPGA系統產品之電源，週邊，記憶體等完整電路  

2.研究合適通訊設備的通訊類演算法  

3.如測試員反應通訊設備若軟體或韌體程式有誤則進行程式除錯  

4.系統檢討，如何做改善及維護  

5.工程規劃設計、設備管理維護

1. Sensor AFE design 

2. ADC design

1. ESD HV 元件及電路開發 

2. TP/TDDI Driver IC ESD Floor Plan & TDDI Module ESD 改善 

3. 小型類比AIP及IO Driver維護

【工作內容】 

AC/DC PMIC Design： 

1.Responsible for AC/DC design 

2.Switching charger, SR, PWM IC design 

3.Fail Analysis 

4.Design document and debugging report 

【工作經驗】 

1.Familiarity with analog circuit and/or IC design including op-amps, DACs, ADCs, LDOs is also desirable. 

2.Experience with analog circuit modeling and simulation tools(e.g. Simplis, HSpice, etc.) 

3.Familiarity with AC/DC Flyback circuit design is plus. 

【工作地點】新竹市新北市

- Lead the architectural definition of each design, defining the system data flow, connectivity and performance required to deliver innovative solutions for the wireless communication system. 

- This position will require substantial cross-functional interaction with the algorithm, software, and systems. 

- Integrate/design elements of the SOC processing fabric including CPU, high-speed interfaces, memory interconnect, top-level clock and reset structures etc.. 

- Work with design, verification, implementation and validation engineering to develop project execution plan and schedule management. 

- Communicate with internal teams and provide suitable test architecture planning for production and verification.  

- Assist DFT structure implementation 

- Working with test engineers to bring up test vectors on test-house/silicon

職責要求 

1.類比IC設計 

2.團隊管理 

任職資格 

1.英文中等，大學以上微電子/電子工程/電機工程/半導體物理系所 

2.五年以上類比IC設計工作經驗 

3.熟悉積體電路版圖和半導體器件

1. 完成系統設計，配置儀器，尋求最佳方案 

2. 完成電路板的電路圖和PCB設計開發 

3. 完成專案的接線圖設計開發 

4. 解決專案開發與驗證過程中的問題，使設計能穩定並符合設計規範 

5. 完成設計項目相關文檔。 

6. 精密量測儀器電路設計(LCR meter, DSO, DMM, ...)