研究所以上電機、資訊、應數相關系所畢，有興趣從事觸控晶片韌體設計開發與演算法校調。熟悉C/C++，或熟悉SoC、嵌入式系統架構，具晶片韌體、演算法開發經驗者尤佳。 工作內容： 1. Develop and maintain touch firmware. 2. Develop and tuning touch algorithm. 3. 依任務需求配合國內外出差。

1.熟Layout Edit Tool操作 2.熟Physical Verification Tool操作 3.具相關工作經驗者尤佳 4. 具 Digital Analog Memory IC Layout2. 熟悉Tool的運用 5. 可接受外派新竹縣市 6.APR ROUTING ※無經驗可，歡迎相關科系畢業生加入我們的行列※

1. IC設計流程自動化開發與維護 2. EDA軟體/iPDK安裝與管理 3. 評估EDA軟體及矽智財 (Silicon IP) 需求 4. 協助提供學界EDA軟體及矽智財使用服務並提供技術支援 5. 其他主管交辦事項

1.負責半導體IC設計、先進封裝技術、CMP製程整合、品質管理 Responsible for semiconductor IC design, advanced packaging, CMP integration, and quality management. 2.產品領域為消費性電子等 Focus on consumer electronics products. 3.工作地點為台北/新竹/台中 The job is based in Taipei, Hsinchu or Taichung.

針對電子廠SMT、DIP製程所須的輔助治具，因應客戶端提供的PCB版實版或gerber大小須求, 設計繪圖，透過電腦操作，下路徑條件給傳送到CNC機台銑製.

研究所以上電子、電機、資工相關系所組畢。 職缺需求： 1. Familiar with Verilog, Perl, synthesis flow and FPGA flow. 2. Familiar with HW/SW co-simulation flow. 3. Chip architecture, clock tree planning and low power design.

電子電路、微電腦電路設計研發。電腦軟韌體研發設計。 應用：光譜儀、化學分析儀器、半導體光電生產製造應用之分析量測儀器研發設計，電子∕微電腦電路、程式軟體研發設計

1. 電子電路設計 設計及測試『精密光學儀器』之電子及控制電路，包括『類比、數位及微處理機╱微電腦』等不同型態、組合之電子電路。 2. 微電腦軔體(Firmware)／軟體設計 設計及測試『精密光學儀器』之『操作功能軟體』，包括驅動程式(Drivers)，I／O 控制，顯示器(LCD/LED, Graphical Display)，鍵盤、操作甚至數學模擬等。設計及撰寫程式 3. 新產品(Prototype)之製作組裝、測試。

1. 進行射頻低雜訊放大器LNA電路架構評估 2. 進行射頻低雜訊放大器LNA電路模擬、設計及量測。 3. 臨時交辦事項。

英業達近年進攻各種 AI 邊緣運算應用領域，我們是英業達 AI 晶片設計研發團隊，具備多年 AI 與 Processor IC 設計經驗，現正積極投入類神經網路加速器 IP 研發。 我們主要工作為應用 Verilog 與 Python，導入來自國際知名 GPU 公司的設計觀念，開發極具競爭力的 AI processor IP，建立完整的 Hardware / Software Co-sim 的環境，所有軟硬體皆 in-house 獨立自主研發，2023 年推出已被數家台灣知名上市 IC 設計公司採用，市場需求踴躍；2024年也於兩家上市 IC 設計公司的 AI 高整合晶片達到 First Cut Work 目標，並通過系統性驗證。現正積極擴大招募新血，歡迎對 IC 設計、CPU 開發、AI 加速器開發有熱誠的朋友加入！ 主要工作內容如下： 1.FPGA RTL coding. 2.Verilog RTL coding & System Verilog Testbench coding. 3.Bring up FPGA test environment and system integrated test. 4.Synthesis, formal checking, & Physical implementation evaluation.

職責內容說明: 01.系統/設備電路控制設計與電控配盤配線規劃。 02.系統/設備電路元件選用，電料BOM表的建立及管理。 03.設備電路圖繪製及修改(AutoCAD經驗者佳)。 04.新開發設備電路相關測試、修改。 05.協助電控相關作業之處理。 06.指導生產線電盤製造及設備電路佈局。 07.可配合國內外出差。 08.其他主管交辦事項。

研究所以上電子、電機、資工相關系所組畢，熟悉或有興趣從事數位訊號處理(DSP)演算法，應用於Touch panel等領域。熟悉C/matlab，熟悉影像處理者尤佳，資深工程師需具三年以上工作經驗。

☑️電路設計與分析 (1)依據車輛規格設定之子系統規格原理進行整車車輛電路設計，包括主電源系統、充電系統、動力與車輛控制相關系統等。 (2)進行電路分析、仿真和驗證，確保設計滿足性能、效率和安全標準。 ☑️電路圖紙製作 (1)製作電動巴士電路的詳細圖紙和文件，包括原理圖佈局。 (2)確保圖紙符合公司內部標準和行業規範。 ☑️技術支持與問題解決 (1)提供技術支持，解決在設計和製造過程中遇到的電路相關問題。 (2)與其他團隊協作，解決集成和測試階段出現的問題。 ☑️產品改進和創新 (1)參與產品改進和創新項目，提出並實施新的電路設計方案。 (2)評估新技術和材料，以提高產品性能和成本效益。

職務類別：電機技師／工程師、電子工程師、EMC／電子安規工程師 學歷要求：學士(含)以上學歷畢 科系要求：不拘 語文條件：多益成績450分以上或具相關能力證明者(托福、雅思、全民英檢等)。 相關經驗：2年以上從事認證相關的事務或測試，熟電池系統或電力系統相關法規尤佳。 電腦技能/證照：Office 出差外派：需出差 工作內容：1.針對產品取證需求洽詢適合的認證公司。 2.針對送測的產品準備認證所需的文件及時程管理。 3.針對測試過程的問題解析及找求對策。 4.研讀相關法規並應用之。 5.產品相關認證報告審查。 6.主管交辦事項。 7.協助產品測試。 服務地點：五股 意者請至台塑企業人才招募網站https://hr.fpg.com.tw登錄履歷，合者約試，不合者恕不通知。

1. 協助開發高速序列基頻晶片，並能獨立閱讀相關協定文件及規劃電路架構。 2. 協助建置及驗證FinFET混訊設計環境。 3. 其他臨時交辦事項。

1. 高速data converter (ADC/DAC)設計驗證 2. FinFET data converter、SerDes、PMIC等電路設計驗證 3. 其他臨時交辦任務

【本職缺僅接受台積電官方網站投遞】 請至台積電官方網站投遞個人履歷表，此職缺履歷登錄網址: https://careers.tsmc.com/careers/JobDetail?jobId=15396&source=1111&tags=domestic+campus+2025_1111 Established in 1987 and headquartered in Taiwan, TSMC pioneered the pure-play foundry business model with an exclusive focus on manufacturing its customers’ products. In 2023, the company served 528 customers with 11,895 products for high performance computing, smartphones, IoT, automotive, and consumer electronics, and is the world’s largest provider of logic ICs with annual capacity of 16 million 12-inch equivalent wafers. TSMC operates fabs in Taiwan as well as manufacturing subsidiaries in Washington State, Japan and China, and its ESMC subsidiary plans to begin construction on a fab in Germany in 2024. In Arizona, TSMC is building three fabs, with the first starting 4nm production in 2025, the second by 2028, and the third by the end of the decade. 因為期待無限可能，所以選擇台積。 台積致力於營造具挑戰性、可以持續學習而又有樂趣的工作環境，提供同業平均水準以上的薪酬與福利。 加入台積，您將與世界一流的優秀夥伴共事，透過最先進的製程技術，成就改變世界的大事，所有突破與創新，都有一份我們的努力。 歡迎「志同道合」的你，透過本計畫提前完成〝線上應徵〝註冊履歷，符合資格者，將享有優先面試的機會唷！ 如您對台積電2025校園徵才計畫感興趣，歡迎報名參加，以掌握台積趨勢、組織概況與求職撇步。 此外，我們將安排五場線上說明會，分別於3/14、3/18、3/25、3/27、3/28舉行，報名連結：請參考官網連結 (採線上報名，報名成功後將由系統自動發送活動通知信件，可重複報名不同場次。) 請優先線上應徵此「校園徵才活動」，如您已有求職偏好職缺，再根據以下職位額外投遞2至4個職位。 ▋歡迎志同道合的夥伴，一起加入台積 ▋世界上的每一個夢，都由我們來圓夢 TOGETHER, WE GROW! TSMC offers a wide variety of fulfilling careers and opportunities across our organization in many different locations. By joining TSMC, you will work with the best team in the industry and achieve your full potential through a comprehensive and systemized learning program here. We are devoted to achieving technology advancement, pursuing manufacturing excellence, and optimizing customer service. You are welcome to submit your resume online to apply for the following job openings for the 2025 TSMC Campus Recruitment. Qualified candidates will have the opportunity for priority interviews. Don‘t miss out! If you are interested in joining TSMC, don’t miss our 〝TSMC 2025 Campus Recruitment Online Briefing Session〝, which will include an introduction to our company, industry trends, career opportunities, and life at TSMC. The sessions will be held on Mar. 14, Mar. 18, Mar. 25, Mar. 27 and Mar. 28. Registration link: Please refer to the link in this job posting on our career site. (The event system will automatically send an email confirmation upon successful registration.) Please apply online for the 〝2025 TSMC Campus Recruitment〝 first. If you have preferred job openings, additionally apply for 2 to 4 positions listed below. 2025 台積電校園熱門職缺 TSMC Campus Recruitment Job : R&D (研究與發展組織專區) 1-1 Research and Development Engineer (R&D) 1-2 Design and Technology Platform Engineer (DTP) 1-3 More-than-Moore Specialty Technology R&D Engineer (MtM) 1-4 Integrated Interconnect & Packaging Engineer (IIP) 1-5 Pathfinding for System Integration Engineer (PSI) Operations (營運組織專區) 2-1 Process Integration Engineer (PIE) 2-2 Process Engineer (PE) 2-3 Equipment Engineer (EQ) 2-4 Intelligent Manufacturing Engineer (IMC/MFG) 2-5 Facility Engineer (FAC) 2-6 Product Engineer (PE) 2-7 Advanced Packaging & Testing Engineer (APTS) 2-8 Quality & Reliability Engineer (Q&R) 2-9 Module Associate Engineer (MAE) 2-10 Technician Strategy & Supporting (策略暨支援組織專區) 3-1 Information Technology Engineer (IT) 3-2 Corporate Planning Organization (CPO) 3-3 Materials Management & Risk Management Engineer (MM&RM) 3-4 Human Resources Specialist (HR) 3-5 Finance & Accounting Specialist (FIN)

1. FinFET 混訊電路(DAC、ADC等)架構評估。 2. FinFET 混訊電路(DAC、ADC等)電路模擬、設計及量測。 3. 其他臨時交辦事項。

Job Responsibilities  Work closely with circuit designers to complete the physical layout and its verification across different country ‒ Receive a schematic from an Analog IC Designer and use a CAD tool to graphically design the layers of that schematic. ‒ Use problem solving & strong communication skills, , experience, and creativity to layout circuits that meet size, schedule, and performance specifications  Run physical design verification tools to debug, improve, and verify layout blocks.  Ability to work independently & Collaborate with team members on continuous improvement opportunities in the flow, layout techniques, and design methodologies.  Each project can last from a couple months to a year and a half. ‒ You will likely work on just one project in that time, but may be asked to switch to something else if priorities change. Your flexibility is appreciated. Job Requirement  Bachelor’s degree in Computer Science, Electrical Engineering or related fields with 3~5 years layout experience ‒ Including at 1~2 years in FINFET process node. 5nm/3nm is preferable  Or 5+ years experience in IC layout design, especially ≥2 years in FINFET process node. 5nm/3nm is preferable  Full-custom circuit layout/verification. Experience in one or more of the following area is preferable ‒ Mixed signal/analog/high speed layout, e.g. SerDes, ADC/DAC, PLL, etc  Familiar with Cadence Virtuoso environment and various industry physical verification tools (DRC,LVS, etc) ‒ Proficient at debugging/fixing LVS/DRC errors • Experience with EMIR analysis, ESD, antenna and related layout solutions • Must have strong communication skills and be a team player

職責要求 - RTL/Logic Integration and Verification - Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for the blocks and the top level including SOC. - Use cdc tool to check RTL/SDC quality - Hands-on experience on post-silicon debug 任職資格 - Knowledge and design experience of digital flows & FPGA validations - One of the Key Serdes protocol (PCIe, SATA, USB, VBO, MIPI etc.) - Knowledge and design experience of PCS