
此職缺的所有相似工作:
(共13筆)
高效能處理器-產品工程師
聯發科技股份有限公司
新竹市東區|面議(經常性薪資4萬/月含以上)展開收合CPU IC 產品發展, 產品量產管理與良率改善, 除錯與問題的解決
要求條件
- ● 資訊工程學類,電子工程學類,電機工程學類 相關科系
測試量產品質資深工程師/技術副理
聯發科技股份有限公司
新竹市東區|面議(經常性薪資4萬/月含以上)展開收合1. Burn in process flow set up & qualification plan
2. Qualification failure electrical & physical analysis
3. Product reliability concern engagement with customer
4. New test supplier audit & qualification
5. Testing house supplier quality & reliability management (Quality incident handling, PCN, regular audit, score card, etc.)
6. New product/technology introduction quality & reliability management
7. Testing house supplier quality improvement project
要求條件
- ● 電機工程學類,其他工程學類,電子工程學類 相關科系
產品品質工程師
聯發科技股份有限公司
新竹市東區|面議(經常性薪資4萬/月含以上)展開收合1. Conducting quality check procedures to ensure high-quality deliverables.
2. Coordinating product quality issue to provide best-fit disposition for quality event impact material.
3. Ensure lessons learned from prior projects are used to improve quality management process.
4. Customer quality communication and RMA/FA management.
要求條件
- ● 電機工程學類,電子工程學類,工業工程學類 相關科系
DFT測試設計工程師
聯發科技股份有限公司
新竹市東區|面議(經常性薪資4萬/月含以上)展開收合對於DFT晶片測試有興趣者,特別是 Automotive low DPPM DFT 以及 RISC-V DFT 領域,
負責開發與實行DFT流程,以降低測試成本、提高產品品質為目的
As a member of DFT engineering team, the candidate will develop methodologies and implement DFT for pre/post-silicon DFT flow and contribute to Automotive/RISC-V product test quality.
Work with senior engineers across disciplines (DE, IMP, PE, TE) to meet low cost and high quality testing
要求條件
- ● 電機工程學類,電子工程學類,資訊工程學類 相關科系
Memory Packaging Technical Manager
聯發科技股份有限公司
新竹市東區|面議(經常性薪資4萬/月含以上)展開收合Product 2.5D/3D/3.5D heterogeneous package development, LPDDR/HBM/IPM development for advanced package, product memory roadmap, package memory architecture , customized HBM development
Senior Testing Engineer/Manger (CP/FT/SLT/Burn-in)
聯發科技股份有限公司
新竹市東區|面議(經常性薪資4萬/月含以上)展開收合1.CP/FT/SLT testing flow development
2.負責CP/FT/SLT/Burn-in 測試配件開發與驗證
要求條件
- ● 電機工程學類,電子工程學類,資訊工程學類 相關科系
平台技術開發
聯發科技股份有限公司
新竹市東區|面議(經常性薪資4萬/月含以上)展開收合1. Develop systematic methodology to alleviate design challenges, including FIP development, synthesis, DFT, physical implementation, sign-off, process what-if assessment, system performance evaluation, in advanced nodes or package.
2. Closely work with foundry and EDA vendors to define innovative HPC, Chiplet design methodologies.
3. Explore new circuit architecture, EDA features and define improvement direction from MTK product requirements.
- 精選精選職缺
- 1天企業預估回應您的時間為「1個工作天」(2~7天以此類推)
- 急此職務急徵人才
- 習企業實習職缺
- 替研發替代役職缺
- 身接受身障職缺
- 職職場新聞,企業有發布新聞稿,文章,活動等訊息
- 溫溫馨職場,企業有提供職場環境及公司文化等簡介
