電源管理系統應用工程師

1. Package related structure stress analysis including warpage, material study. 

2. Package and board level stress modeling for TCT, drop and vibration. 

3. IC and package thermal analysis, modeling and characterization 

4. Chip-Package-PCB thermal co-simulation and design. 

5. System level thermal simulation 

6. System level stress simulation

IC 測試開發工程師 

負責高速數位、類比晶片測試程式開發(AP/compu AI/ASIC/…)，產品特性異常分析與改善 

新產品導入量產與生產良率測試時間優化 

俱獨立帶產品作業為佳。

The candidate will design, supervise layout, help characterize transceiver front-end circuits for WiFi and Bluetooth production.

Analog/Mixed-signal circuit design

28nm及以下先進製程(含FinFET) IO電路和ESD防護設計, 工作內容包含  

(1) GPIO電路設計(包含ESD/LU防護) 

(2) 特殊應用IO (SD3.0/SIM card/eMMC等)電路設計(包含ESD/L防護)  

(3) 高速IO和特殊應用IO在事業部專案上展開和執行 

- Advance node (28nm and beyond, including FetFET) IO circuitry and ESD protection design covering fields for  

(a) General purpose IO circuit design (with ESD/LU protection)  

(b) Specialty IO (SD3.0/SIM card/eMMC etc.) circuit design (with ESD/LU protection)  

(c) Project related implementation for high speed/specialty IO Interface - High speed IO, specialty IO circuit design, ESD protection circuit design and simulation.  

Work with project leader, layout, packaging and system engineers to meet design and system specifications.  

Work with IO library modeling, characterization teams closely for IP release.

- 負責⼿機或modem模組的參考設計 

- 設計開發驗證平台(EVB/phone)，產出相關設計和⽣產文件(線路 

圖、物料清單、⽣產文件)，與CAD團隊實現PCB設計。 

- 驗證平台製作與測試 

- 提供技術⽀持，協助客⼾進⾏產品開發和⽣產。 

- 分析客⼾需求或問題，以提供技術指導或解決⽅案，及後續產品的設計參考。

1. 高速信號介面及系統電源應用規劃整合、除錯等手機系統應用. 

2. Baseband系統驗證方法開發、電源規格訂定及驗證規劃 

3. 客戶參考設計文件訂定及量產相關技術支援.

1. WiFi/BT/GPS/FM connectivity IC驗證及系統應用 

2. PMIC or PCIe 系統設計及驗證  

3. Connectivity 系統性能優化及驗證 

4. Connectivity參考電路設計及驗證 

5. 協助客戶量產過程時提供技術支援

1. 平台電源管理系統架構設計與規格定義, 包含功耗/溫度/性能等系統分析. 

2. 系統應用詳細電源需求與控制架構之分析與優化 

3. 電源管理芯片規格制定與新技術之開發.

Work in Analog/Mixed-Signal Modeling and Verification Methodology Development group to establish, streamline and enhance new and existing AMS Behavioral Modeling related development method, coding and validation process and integration flows, and work hands-on with AMS IP Teams for AMS Behavioral Modeling flow and process experiments, demonstrations, adaptions, and deployment. The candidate will work with AMS IP teams including digital design, analog design, analog behavioral modeling and design verification members, apply and advance existing and evolving AMS Behavioral Modeling methodologies and processes, and contribute to establish and maintain Modeling Platform to ensure High Quality and High Efficiency of Pre-Si AMS Modeling, Validation and Verification delivery towards high quality silicon products. 

• Work in methodology development group to establish, streamline and enhance new and existing AMS Behavioral Modeling related development method, coding and validation process and integration flows. 

• Work with teams to enable deployment of new AMS Behavioral Modeling flow and processes through experiments, demonstrations, adaptions (for real projects in specified areas such as RF, etc) and integration.  

• Document on new flows and processes for AMS Behavioral Modeling. 

• Apply wide range of AMS Behavioral Modeling skills to help and support AMS IP or Chip Teams to establish or enhance new or existing Modeling capabilities, including but not limited to Model Development, Model Validation to ensure Consistency of Behavior with Original Circuit, Integration of Models into various Verification Environment, fixing Modeling issues found in simulation, etc.  

• Contribute to continuous improving on AMS Behavioral Modeling process for better quality and efficiency through methodology and process improvements.  

• Communicate and collaborate with global architecture, design, verification teams to address new needs or requirement on AMS Behavioral Modeling. 

Job Locations: 

• Taiwan:Hsinchu/Taipei 

• India: Bangalore 

• Singapore 

• USA:Santa Clara, CA/San Diego, CA

Work in Analog/Mixed-Signal Design Verification Methodology Development group to establish, streamline and enhance new and existing AMS DV related development method, coding process and integration flows, and work hands-on with AMS IP Teams for AMS DV flow and process experiments, demonstrations, adaptions, and deployment. The candidate will work with digital design, analog design, analog behavioral modeling and design verification teams, apply and advance existing and evolving Digital and AMS Verification methodologies and processes, and contribute to establish and maintain Verification Platform to ensure High Quality and High Efficiency of Pre-Si Verification Delivery towards high quality silicon products.  

• Work in methodology development team to establish, streamline and enhance new and existing AMS DV related development method, coding process and integration flows. 

• Work with teams to enable deployment of new flow and processes through experiments, demonstrations, adaptions (for real projects in specified areas such as SERDES, etc) and integration.  

• Document on new flows and processes for AMS DV. 

• Apply wide range of Digital and/or AMS DV skills to help and support AMS IP or Chip DV Teams to establish or enhance new or existing DV capabilities, including but not limited to developing scalable and portable Test bench, test cases, drivers, checkers, assertions and reference models, and running RTL and Gate Level simulations and reaching all coverage closures.  

• Contribute to continuous improving on AMS DV process for better quality and efficiency through methodology and process improvements.  

• Communicate and collaborate with global architecture, design, verification, and post-Silicon testing teams to address new needs or requirement on DV Support. 

Job Locations: 

• Taiwan:Hsinchu/Taipei 

• India: Bangalore 

• Singapore 

• USA:Santa Clara, CA/San Diego, CA

This position involves developing memory architectures, creating circuit implementation techniques and be an interface with CAD team for full verification and model generation. You have opportunity to know how memory design can be implemented into all Mediatek products.

高速類比 SerDes 電路設計 

Work Location : 新竹/竹北/台北/台南

協助電源管理晶片規格製定, 新 IP 開發規劃及產品驗證協助類比晶片IP開發, 驗證.

MTK電源管理部門設計設計電源管理IC及電源管理單元以滿足各式各樣智慧手機, IOT, 車用, 以及ASIC的需求. 

職缺包含:  

1. DC-DC 轉換器 

2. 線性電壓調節器 

3. 切換電壓調節器