類比Serdes電路設計工程師

1.依據客戶要求完成硬體設計(電路圖,PCB案件電路繪製、佈排線、Bom產出、被動元件選用)。 

2.負責PCB板廠品質確認,進行溝通 

3.量產前出差至客戶端進行PCB訊號校驗 

4.配合客戶軟體工程師完成產品開發任務 

5.具Load Board Layout(封測廠tester V93K, S100, S300愛得萬測試機)相關經驗尤佳 

※本職缺依個人專業年資及學歷經驗核定職務及敘薪。 

※Layout軟體 : PADS, Allegro 。

• Define comprehensive DFT/test architecture for 3DIC and chiplet-based products, including pre-bond, mid-bond, post-bond, final test, and system-level test considerations. 

• Develop test strategy for logic, memory, interconnect, TSV/micro-bump connectivity, repair, redundancy, and yield monitoring. 

• Work with architecture, design, package, product engineering, reliability, and operations teams to ensure testability is built in from the beginning. 

• Drive implementation planning for scan, MBIST, LBIST, boundary test, interconnect test, and diagnosis flows as applicable. 

• Evaluate tradeoffs among coverage, test time, test cost, quality, and production scalability. 

• Support ATE strategy, test access mechanisms, known-good-die methodology, and failure diagnosis for stacked or chiplet products. 

• Establish DFT guidelines, test insertion requirements, and quality metrics for future 3DIC platforms. 

• Lead bring-up and silicon learning feedback loop to improve yield and test effectiveness.

• Define architecture and implementation strategy for die-to-die PHY driver, receiver, IO circuits, and ESD protection schemes for 3DIC products. 

• Lead transistor-level and circuit-level design for high-speed, low-power interface blocks targeting chiplet and 3D integration applications. 

• Optimize IO/PHY design for bandwidth, power, latency, signal integrity, area efficiency, and reliability. 

• Develop ESD protection concepts compatible with fine-pitch micro-bump, TSV/interposer, and advanced package constraints. 

• Drive design verification, corner analysis, reliability validation, and design signoff for IO/PHY/ESD circuits. 

• Support technology evaluation for emerging die-to-die standards and internal interface solutions. 

• Build reusable circuit IP, design guidelines, and implementation know-how for future programs.

• Define and drive PI/SI/Thermal signoff methodology for 3DIC, chiplet, and advanced packaging programs.  

• Lead end-to-end analysis for power delivery network, high-speed signal channels, and thermal/mechanical interaction across die-package-system.  

• Establish signoff criteria, design margins, modelling quality standards, and correlation flow for simulation versus silicon or lab measurements.  

• Work closely with package design, bump/TSV planning, PHY/IO, floorplan, architecture, and product engineering teams to resolve integration issues early.  

• Identify and mitigate risks related to IR drop, SSN, jitter, crosstalk, insertion loss, return loss, EMI/EMC, hotspot formation, and thermal coupling.  

• Drive EDA vendor and tool engagement for modelling, extraction, co-simulation, and signoff automation.

1.PCB 電路及layout 的設計及驗證 

2. 客戶端平台之開發驗證

此(資深)職缺需以軟體/韌體設計的角度，進行聯發科技無線通訊網路相關IC設計方案的韌體白盒測試，包含WiFi、Bluetooth相關的功能。 

需要負責與MAC、PHY、System、SW 等工程團隊合作，進行韌體白盒測試的開發、建置，與問題的除錯分析。 

需要設計與開發不同的韌體測試方法，包含自動化測試的開發與建置，並且不斷的精進改善，以期軟韌體的品質能夠符合內部開發及外部客戶的要求。

1. 負責高速 Serdes相關開發, 包含驗證, 客戶支援 

(熟悉架構, 韌體、除錯、優化及測試等工作項目)  

2. 開發測試自動化  

3. 協同團隊共同完成系統雛型建立及性能優化與調適  

4. 達成客戶端產品導入，並支援產品量產

1. 企業/家用WIFI AP路由器 開發經驗者尤佳  

2. 高速介面應用, 驗證及除錯 e.g. USB, PCIe, xGMII, Ethernet, DDR 

3. 802.11 a/b/g/n/ac/ax/be WiFi SoC及Ethernet SoC驗證, 公板設計及驗證  

4. Power/Thermal/EMI 防治對策  

5. 支持客戶應用及量產導入  

6. 熟悉HW設計的TOOL 如OrCAD, PADS, Allegro

Analog circuit design, including ADC, DAC, PLL, PGA, OPAMP and analog front end circuit design.