封裝技術經理

1.設計測試硬體配件  

2.IC驗證  

3.CP/FT 測試程式開發  

4.量產維護

• New product implementation, especially in Flip Chip related products​ 

• Assembly yield improvement, issue and RMA resolving​ 

• Package technology development and process improvement

1. 2.5D/3.5D package technology development​ 

2. SoC/Memory heterogeneous integration package development​ 

3. Package technology integration, NPI and MP​ 

4. Project management​

CPU IC 產品發展, 產品量產管理與良率改善, 除錯與問題的解決

1. Automotive Packaging development, New product introduction, Mass production, Supplier management.​ 

2. Develop and evaluate the advanced IC Package technology.​ 

3. Collaborate with the assembly subcontractors to complete the technology development.​ 

4. Qualification and yield improvement for the advanced IC Packages.​ 

5. Audit subcontractors.

IC 測試工程師負責工作為: CP/FT ATE 測試程式撰寫與開發 CP/FT 量產導入與維護, 及良率分析 熟悉SOC digital mixed signal/ RF 測試. 熟UltraFlex/V93K 者佳.

1. Burn in process flow set up & qualification plan​ 

2. Qualification failure electrical & physical analysis​ 

3. Product reliability concern engagement with customer​ 

4. New test supplier audit & qualification​ 

5. Testing house supplier quality & reliability management (Quality incident handling, PCN, regular audit, score card, etc.)​ 

6. New product/technology introduction quality & reliability management​ 

7. Testing house supplier quality improvement project

1. IC封裝/晶圓凸塊技術開發與管理  

2. 與封裝廠合作完成規劃之技術開發  

3. 先進封裝技術開發,品質驗證與生產良率管理  

4. 定期與不定期執行bumping/fan-out/WLCSP廠品質稽核

對於DFT晶片測試有興趣者，特別是 Automotive low DPPM DFT 以及 RISC-V DFT 領域， 

負責開發與實行DFT流程，以降低測試成本、提高產品品質為目的 

As a member of DFT engineering team, the candidate will develop methodologies and implement DFT for pre/post-silicon DFT flow and contribute to Automotive/RISC-V product test quality. 

Work with senior engineers across disciplines (DE, IMP, PE, TE) to meet low cost and high quality testing

Product 2.5D/3D/3.5D heterogeneous package development, LPDDR/HBM/IPM development for advanced package, product memory roadmap, package memory architecture , customized HBM development

1.CP/FT/SLT testing flow development  

2.負責CP/FT/SLT/Burn-in 測試配件開發與驗證

1. 先進製程技術製程開發  

2. 先進封裝技術開發

1. Develop systematic methodology to alleviate design challenges, including FIP development, synthesis, DFT, physical implementation, sign-off, process what-if assessment, system performance evaluation, in advanced nodes or package.  

2. Closely work with foundry and EDA vendors to define innovative HPC, Chiplet design methodologies. 

3. Explore new circuit architecture, EDA features and define improvement direction from MTK product requirements.

• 新產品導入量產 (IC 封裝部分) 

• 良率持續改善 

• 解決製程異常, 工程問題 

• 技術開發與製程改善

先進封裝技術開發 

1. 先進新產品導入技術開發 (新產片試產規劃, DRC/DRM檢驗, DOE及良率改善規劃, 量產區間及良率分析)  

2. 熟悉先進chiplet及3DIC封裝技術開發 

3. 晶圓級與面板級先進封裝結構設計

1. DFT architecture exploration & evaluation for next-gen process node & package technology of MediaTek: 

* Scan chain insertion & ATPG pattern generation 

* Pattern validation through simulation & silicon analysis(pass/fail, shmoo, fail log, etc.) 

* Diagnosis to help manufacture process improvement 

2. Co-work with SoC architect, RTL designer, physical design engineer, and package engineer to define best architecture for 3D-IC: 

* PPA(Performance/Power/Area) impact analysis & mitigation via DFT innovation 

* Develop & integrate DFT-related RTL design modules to test chip

IC 產品發展, 產品量產管理與良率改善, 除錯與問題的解決