手機DRAM/Storage系統應用工程師

1.AI系統硬體規劃：系統規格與設計需求收集 

2.AI系統硬體設計：負責設計和開發硬體系統架構，包括電路設計、元件評估與選擇、客製化元件規劃。  

3. AI系統硬體驗證與測試：確認硬體系統正常運作，包含驗證與測試。 

4. 跨組織合作：與IC design team、system team、SI/PI team與layout team等等合作，完成系統設計、製作與驗證。 

5.客戶與相關廠商支援：包含技術文件撰寫、客戶參考設計支援、on site支援等等。

1. Package design and planning of various product.  

2. Design & layout of BGA substrate.  

3. Co-work with package houses for package design 

4. Development of advanced package technology.  

5. Package design platform development.

- 架構與規格設計： 定義與設計射頻積體電路 (RFIC) 系統架構，並制定先進通訊解決方案的詳細技術規格。 

- 校準與控制開發： 開發並驗證射頻校準演算法與射頻系統控制流程，以優化收發器在各種環境下的效能表現。 

- 通訊系統與數位訊號處理： 設計無線通訊系統，並針對射頻性能優化與非理想特性補償，開發專用的數位訊號處理 (DSP) 演算法。 

- Architecture & Specification: Define and design RFIC system architectures and detailed technical specifications for advanced connectivity solutions. 

- Calibration & Control: Develop and verify RF calibration algorithms and RF system control flows to optimize transceiver performance across various conditions. 

- Communication System & DSP: Design wireless communication systems and implement digital signal processing (DSP) algorithms specifically tailored for RF performance enhancement and impairment compensation.

1. 無線 RFIC 類比電路設計. 

2. 頻率合成器, 鎖相迴路, 壓控振盪器, 晶體振盪器, 除頻器 設計.

設計以資料中心和人工智慧產品為導向的高速Serdes連接PHY架構。該職位的主要職責是為世界級客戶設計並交付ASIC產品。您將參與打造低功耗、高性價比且高速的Serdes PHY設計。您將有機會拓展視野，與來自多個國家的同事合作。此職位所需的專業知識包括數位通訊設計（均衡器、有限脈衝響應濾波器）、類比設計（鎖相環、類比數位轉換器、校準）和系統單晶片（SoC）設計（微控制器、匯流排協定）。

(請留意：為加快面試安排時間，僅限定投遞5個職缺)我們在找這樣的你：對行動通訊、無線及寛頻連結、家庭娛樂晶片解決方案有濃厚興趣；勇於表達意見，以團隊成功為目標，面對困難不輕易放棄，總是在想更好的做法，擁有創新及不斷學習的精神。聯發科技邀請您，與全球最頂尖的菁英一同合作，彼此激盪最新的創意與解法，共同挑戰每一個不可能

1. IEEE 802.3 Ethernet PHY & transceiver architecture & algorithm design 

2. Digital signal processing of mixed-signal design 

3. System simulation/model design for pre-silicon verification 

4. System & algorithm design/simulation of high-speed I/F SerDes 

5. Make contribution in standard organizations

1. Serdes PMA IP architecture planning 

2. Serdes PMA IP RTL coding 

3. Serdes PMA IP front-end and back-end integration 

4. Co-work with PCS and MAC design team and DV team for IP verification 

5. Co-work with Analog design team for PHY co-simulation 

6. Co-work with Algorithm team for algorithm implementation and bit-true verification

1. 高速 SERDES SIPI 分析和整合 

2. Core power PI 分析和整合

1.PCB power related hardware design：Resonsible for design and develop hardware including circuit design, component evaluation and selection, customized component planning, layout review, etc. 

2. System specification and design requirement collection. 

3. System hardware verification and testing: function verification and power quality measurement. 

4. Cross-organizational collaboration: Collaborate with IC design team, system team, SI/PI team, layout team, etc. to complete system design, production and verification. 

5. Customer and related manufacturer support: including technical document writing, customer reference design support, on site support, etc.

• Chip to Chip 介面類比 PHY 電路，例如 UCIe 標準或客製化的 Die to Die 連結類比電路設計 

• HBM/DDR/LPDDR類比PHY電路設計與混合模式/高速電路設計等。

1.CPO SERDES 系統開發​ 

2.CPO Optical系統開發

1. Serdes/High speed interface related PHYD IP architecture planning. 

2. Serdes/High speed interface related PHYD IP RTL coding.  

3. Serdes/High speed interface related PHYD IP front-end and back-end integration.  

4. Co-work with MAC design team and DV team for IP verification.  

5. Co-work with Analog design team for PHY co-simulation.

1. DFT architecture exploration & evaluation for next-gen process node & package technology of MediaTek: 

* Scan chain insertion & ATPG pattern generation 

* Pattern validation through simulation & silicon analysis(pass/fail, shmoo, fail log, etc.) 

* Diagnosis to help manufacture process improvement 

2. Co-work with SoC architect, RTL designer, physical design engineer, and package engineer to define best architecture for 3D-IC: 

* PPA(Performance/Power/Area) impact analysis & mitigation via DFT innovation 

* Develop & integrate DFT-related RTL design modules to test chip

(請留意：為加快面試安排時間，2026校招僅限定投遞5個職缺)我們在找這樣的你： 資工/資管/電子/電機/電信/通訊/電控相關研究所背景，對行動通訊、無線及寛頻連結、家庭娛樂晶片解決方案有濃厚興趣的2026年應屆畢業生。 勇於表達意見，以團隊成功為目標，面對困難不輕易放棄，總是在想更好的做法，擁有創新及不斷學習的精神。 聯發科技邀請您，與全球最頂尖的菁英一同合作，彼此激盪最新的創意與解法，共同挑戰每一個不可能。

(請留意：為加快面試安排時間，2026校招僅限定投遞5個職缺)我們在找這樣的你： 資工/資管/電子/電機/電信/通訊/電控相關研究所背景，對行動通訊、無線及寛頻連結、家庭娛樂晶片解決方案有濃厚興趣的2026年應屆畢業生。 勇於表達意見，以團隊成功為目標，面對困難不輕易放棄，總是在想更好的做法，擁有創新及不斷學習的精神。 聯發科技邀請您，與全球最頂尖的菁英一同合作，彼此激盪最新的創意與解法，共同挑戰每一個不可能。

1. Package related structure stress analysis including warpage, material study.  

2. Package and board level stress modeling for TCT, drop and vibration.  

3. IC and package thermal analysis, modeling and characterization  

4. Chip-Package-PCB thermal co-simulation and design.  

5. System level thermal simulation 6. System level stress simulation

1. Wired or wireless communication system transceiver architecture or algorithm design. 

2. RF/Analog front end & baseband system spec definition 

3. Channel and impairment modeling 

4. Baseband algorithm development 

5. System performance verification

1. CoWoS和2.5D封裝技術開發 

2. 3D封裝技術開發 

3. CPC/CPO封裝技術開發 

4. 封裝技術整合和NTO管理

1. Package related structure stress analysis including warpage, material study. 

2. Package and board level stress modeling for TCT, drop and vibration. 

3. IC and package thermal analysis, modeling and characterization 

4. Chip-Package-PCB thermal co-simulation and design. 

5. System level thermal simulation 

6. System level stress simulation