Memory Packaging Technical Manager​

1.設計測試硬體配件  

2.IC驗證  

3.CP/FT 測試程式開發  

4.量產維護

• New product implementation, especially in Flip Chip related products​ 

• Assembly yield improvement, issue and RMA resolving​ 

• Package technology development and process improvement

CPU IC 產品發展, 產品量產管理與良率改善, 除錯與問題的解決

IC 測試工程師負責工作為: CP/FT ATE 測試程式撰寫與開發 CP/FT 量產導入與維護, 及良率分析 熟悉SOC digital mixed signal/ RF 測試. 熟UltraFlex/V93K 者佳.

1. Burn in process flow set up & qualification plan​ 

2. Qualification failure electrical & physical analysis​ 

3. Product reliability concern engagement with customer​ 

4. New test supplier audit & qualification​ 

5. Testing house supplier quality & reliability management (Quality incident handling, PCN, regular audit, score card, etc.)​ 

6. New product/technology introduction quality & reliability management​ 

7. Testing house supplier quality improvement project

對於DFT晶片測試有興趣者，特別是 Automotive low DPPM DFT 以及 RISC-V DFT 領域， 

負責開發與實行DFT流程，以降低測試成本、提高產品品質為目的 

As a member of DFT engineering team, the candidate will develop methodologies and implement DFT for pre/post-silicon DFT flow and contribute to Automotive/RISC-V product test quality. 

Work with senior engineers across disciplines (DE, IMP, PE, TE) to meet low cost and high quality testing

1.CP/FT/SLT testing flow development  

2.負責CP/FT/SLT/Burn-in 測試配件開發與驗證

Develop advanced package technologies for MediaTek‘s HPC business

IC 產品發展, 產品量產管理與良率改善, 除錯與問題的解決