2026暑期實習生_竹科(刊期已經結束)

1.Spice model generation and verification for advanced and specialty technologies 

2.Spice Model Parameter Extraction 

3.Test key design 

4.Internal and external customer support 

5.Advanced modeling tools, extraction algorithms and model equation benchmarking

工作項目：  

1.負責AFE IP功能與規格驗證，確保設計品質  

2.與團隊討論並定義工程規格，參與產品規格制定流程  

3.進行設計工具之分析、研究與基準測試(Bench Mark Test)，提出優化建議  

4.使用Matlab/Simulink模擬軟體建立PLL/ADC/DAC行為模型的分析  

5.AFE相關的Research, Study and Paper Work  

6.自動化開發與維護  

7.發想並完成發明專利申請，提升技術競爭力 

應徵條件:  

1. 研究所以上電機電子相關系所畢業 

2. 熟PLL/ADC/DAC等電路的特性及驗證 

3. 具Python自動化開發經驗與熟悉車用驗證者尤佳。

【2026年力積電人才預聘（暨）實習計畫】 

對半導體產業充滿興趣，想要開啟職涯冒險嗎？ 

＼歡迎加入我們的「預聘實習計畫」／ 

除了實際體驗工程師的工作以外， 

還有豐富的培訓課程、專案發表機會，讓你快速提升職場競爭力！ 

最重要的是～ 

表現優秀就有機會拿到「預聘offer」，讓你畢業即就業喔！ 

▎招募對象： 

電子／電機／光電／物理／材料／化學（工）／機械等理工系所－大三以上之在學學生 

▎職缺內容： 

✦ 實習內容：製程／設備／整合／研發工程師 

✦ 實習期間：學期實習（每週至少三天）；暑期實習（週一至週五） 

▎計畫時程： 

✦ 2026年4－6月學期實習 

－申請時間：即日起－2025／12 

－面談時間：2025／11－2026／01 

✦ 2026年7－8月暑期實習 

－申請時間：即日起－2026／03 

－面談時間：2026／02－2026／04 

▎計畫亮點： 

1. 實習月薪 NTD $35,000 ~ 40,000 

2. 「部門主管及HR導師制度」讓你快速融入力積電大家庭！ 

3. 「實務專案 & 多元課程」累積經驗和實力 

4. 畢業前優先獲得正職機會！（試用期滿發放獎金NTD $20,000 ） 

5. 可使用健身房、運動場、KTV室、員工餐廳等豐富設施 

6. 實習年資併入正式年資，晉升更有利 

▎報名方式： 

透過「1111人力銀行」或「官網」投遞履歷（搶先獲得面談機會～） 

https://wwwmgt/zh-tw/join/index/other?d_target=bottom-link-title 

2026年力積電預聘實習計畫！歡迎你的加入 ( ੭ ˙ᗜ˙ )੭ ٩꒰｡

工作內容: 

1.新產品開發缺陷分析 

2.製程異常分析與改善 

3.新製程實驗評估 

4.班別:常日班、需假日/小夜輪值

1.元件電性測試與分析 

2.TPL (Test Programming Language) 撰寫與 Debug  

3.Device tuning and model prepare  

4.跨部門溝通合作 

5.新產品電性測試 testkey 開發

1. Project schedule 制定與管控 

2. 協助新產品導入及驗證 

3. 熟悉 WP/AP/WT/FT 流程 

4. 熟悉產品應用及規格

1.邏輯元件製程開發 

2.整合製程 

3.良率提升 

4.光罩設計

1.邏輯元件開發 (LV/ SRAM device design and development)  

2.元件開發工作 (EDR, SPICE, Reliability, Testkey design, WAT analysis, Device characteristics) 

3.良率與製程相關性分析 (Yield & process correlation analysis)

1. 新產品導入 

2. 控制線上產品及異常分析 

3. 產品良率的提昇 

4. 元件電性測試與分析

1. DRAM research and layout design/ tape out. 

2. DRAM process flow setup and optimize. 

3. DRAM architecture & characteristic development for advance generation 

4. DRAM process tuning(co-work with module) and improvement

1. 客戶與公司內部單位的溝通橋樑 

2. 負責處理客戶產品pre-tapeout, tape-out, pilot run到mass production的相關事務

1. Discrete Device 

2. Power MOSFET 

3. TSV, IGBT 

4. 常日班，需配合假日值班

1.新產品導入 

2.控制線上產品及異常分析 

3.產品良率的提昇 

4.元件電性測試與分析

Please apply for this position on NXP official website: https://pse.is/836k2a 

Job Responsibilities: 

APAC Central Competence Team works with external foundries to ensure stable chip supply for business lines across NXP.  

The primary responsibility of this role is to locally drive the lead products ramp up under new technology introduction (NTI). 

The key areas of responsibility of the jobholder are: 

1. Close collaboration with foundries, NXP technology groups, the business lines and various other stakeholders to qualify and release process 

2. Front end process safe launch owner. Closely work with foundries at ramp up phase and drive for manufacturability and yield improvement. 

3. Interface with key customers on critical projects. 

4. Lead and steer the projects towards timely completion to support NXP business needs 

5. Main decision maker on subjects related to process integration, striking a good balance between the various dynamics in a project; not limiting to technical judgement, resource planning, project schedule, logistics, supplier relationships etc 

Requirements / preferences: 

1. Bachelor or MSc in physics or electrical engineering. 

2. ＞10 years of experience with front-end IC process integration, working in foundries’ production or development teams 

3. In-depth knowledge of IC devices and processes. FinFET and NVM knowledge is a plus. 

4. Strong understanding of yield enhancement techniques and data analysis 

5. Must be fluent in English and Mandarin 

6. Hands on experience in being a lead; leading teams with responsibilities in development / transfer projects or production ramp up. 

7. Good communication skills. Having the ability to influence and steer a discussion 

8. Pro-active working attitude, creative, pragmatic, enterprising and result driven. 

9. Familiar in managing/working with foundries, maximizing leverage from foundries

The key areas of responsibility of the jobholder are: 

- Collaborate closely with foundries, NXP technology teams, and business lines to qualify and release advanced FinFET processes. 

- Provide technical leadership in semiconductor device physics, especially in FinFET architecture and behavior. 

- Interface with internal and external stakeholders on critical development and transfer projects. 

- Lead and steer projects to meet timelines and business objectives. 

- Make key decisions on process integration, balancing technical, logistical, and strategic factors. 

- Support NTI process transfers within foundries and NXP joint ventures 

Requirements / preferences:  

- Bachelor‘s or Master‘s degree in Electrical Engineering, Physics, or related field. 

- Minimum 10 years of experience in semiconductor device engineering, with a strong focus on advanced logic/RF devices. 

- Proven hands-on experience with HKMG and FinFET technologies in production or development environments. 

- Deep understanding of semiconductor device physics, especially HKMG and FinFET. 

- Strong analytical skills in yield enhancement and electrical data analysis. 

- Fluent in English and Mandarin. 

- Demonstrated leadership in development, transfer, or ramp-up projects. 

- Excellent communication and influencing skills. 

- Proactive, pragmatic, and results-driven mindset. 

- Experience working with foundries and leveraging external manufacturing capabilities .

***Please apply for this position on NXP official website: https://pse.is/8ms2kr 

Role Purpose 

Lead the development and optimization of high-voltage (HV) and BCD device architectures. This role requires a deep understanding of device physics and a data-driven approach to ensure industry-leading performance and reliability for power management solutions. 

Key Responsibilities 

－ Device Development: Lead the architecture design and optimization of HV devices (LDMOS, EDMOS, ESD) on 180nm to 55nm BCD nodes. 

－ Physics Analysis: Analyze and optimize Device Physics parameters, including BV, Rdson, SOA, and reliability (HCI/NBTI). 

－ Simulation & Modeling: Utilize TCAD for 2D/3D process and device simulations to accelerate development cycles. 

－ Device Verification: Define verification plans and execute statistical analysis using JMP for DOE and WAT data. 

－ Design Integration: Work within Cadence environments for layout review and test structure design. 

－ Cross-functional Collaboration: Partner with PI and PE teams to resolve yield, reliability, and manufacturing bottlenecks. 

Required Qualifications 

－ Experience: Master‘s or Ph.D. in EE, Physics, or related field with 10+ years of semiconductor industry experience. 

－ Technical Expertise: 

1. Profound knowledge of Device Architecture and Device Physics. 

2. Hands-on experience in 180nm to 55nm BCD process nodes. 

－ Tools: 

1. Expertise in TCAD (Sentaurus / Silvaco). 

2. Expertise in JMP for statistical data analysis. 

3. Proficiency in Cadence (Layout/Virtuoso). 

Preferred Qualifications (Plus) 

－ Advanced Power Devices: Experience with GaN, SiC, or IGBT development. 

－ Silicon Photonics: Knowledge of Photonics integration and device physics. 

－ Domain Knowledge: 

1. Process Integration (PI): Understanding of mask flow and doping profiles. 

2. Product Engineering (PE): Experience in CP/FT data correlation and yield enhancement. 

Competencies 

－ Accountability: Strong ownership of project milestones and outcomes. 

－ Critical Thinking: Ability to identify root causes in complex device failures. 

－ Interpersonal Skills: Effective communication across design and foundry teams. 

－ Data-driven: Committed to objective decision-making through rigorous data analysis.

Role Summary:  

The NVM Reliability team is responsible for characterizing, modeling, and enabling next-generation Non-Volatile Memory technologies, enabling new product creation company-wide. 

Job Responsibility:  

－Interface with foundries and other external suppliers of technology and IP to assess reliability margin to product applications.  

－Establish qualification requirements for new technology and product introduction.  

－Perform rigorous statistical analysis of reliability characterization data. 

－Enable high reliability during volume production by working with product groups to address risk areas. 

－Support business groups with customer requests for technical information, including reliability characterization results, risks assessments, and consultation on issues. 

－Communicate study conclusions and recommendations to internal and external teams.  

Job Qualification:  

－Bachelor‘s, Masters, or Doctoral degree in Electrical Engineering, Applied Physics, or equivalent, with 10 years of industry experience. 

－Experienced in data processing and analysis (e.g. Python, JMP, Matlab, Exensio). 

－Software development experience, such as familiarity with microcontroller software development (C/C++) is desired. 

－Interest in statistics and solid-state device fundamentals, especially as applied to emerging non-volatile memory technologies like MRAM and RRAM.  

－Must be curious, proactive, and detail-oriented. 

－Able to work in a team environment, communicate effectively in English and Mandarin, and solve problems.

瑞昱半導體【科技專才創造力學程實習計劃】將提供本計劃實習生： 

1. 科技專才培育：規劃實習同仁專屬五大面向課程，培養專業、開發思考與創造力。 

2. 賦予研究專題與實質任務。 

3. 科別專責輔導員：每位實習生設有專屬輔導者，協助專業學習及問題引導。 

實習期間：於2026年7月至8月進行專案實習與活動安排。 

實習時間：週一至週五8:30-17:30，週休二日。 

實習地點：瑞昱新竹一廠、二/三廠及生醫廠。 

招募對象： 

大三(含)以上、碩士班或博士班之電子、電機、電信、電控、資工、資科等相關科系在學生，具下列任一條件者佳： 

a. 熟悉 C語言或VB. 

b. 熟悉 Office, OrCAD 

c. 對RF測試、測試程式開發及維護有興趣者。 

d. 對Probe card, Load board電路設計、產品良率的改善有興趣者。