＜Automotive＞Automotive Packaging Engineer/Technical Manager

* 根據積體電路設計流程、半導體器件、良率提升等相關知識進行數據分析  

* 建立人工智慧框架與工作流程，以提升數據運營與分析的生產力  

* 與不同的內部及外部團隊溝通協作，提出策略建議

參與先進製程下ASIC及其他產品的開發與導入。  

支援新產品線，如CPO、IVR、cHBM......等技術的設計、驗證與量產導入。  

與跨部門團隊合作，解決產品開發過程中的技術問題，確保專案順利執行。  

持續追蹤先進半導體製程與新穎封裝技術的產業動態，提供技術建議。

我們誠摯招募具高度熱忱且具備一定經驗的製程與元件開發專才，致力於為聯發科技（MediaTek）的內部產品及客製化晶片（ASIC）開發先進製程平台。 在此職務中，您將負責評估最尖端的半導體製程節點（如 2nm、1.4nm、FinFET、GAA/Nanosheet 等），推動設計與技術協同最佳化（DTCO），並確保晶圓代工廠的製程能力與我們的產品藍圖完美契合，以實現最佳的功耗、效能與面積（PPA）表現。  

主要職責：  

1.技術評估、晶圓代工廠合作對接（Foundry Interfacing）以及製程與元件開發。  

2. 元件目標規格設定，以及標準元件庫（Library）／模型（Model）／製程設計套件（PDK）之對齊與驗證。  

3. 製程客製化與Post-silicon tuning，以最大化產品效能。  

4. 推動製程端之設計與技術協同最佳化（Process DTCO）。  

5. 針對良率（Yield）與可靠度（Reliability）開發DFM。  

6. 先進製程技術之先期研究（Process technology pathfinding）。

負責先進製程產品良率改善,應徵者必須有超過3年以上先進製程開發相關經驗.擁有資料中心晶片良率改善或是高速運算中心晶片良率改善經驗優先考慮

1. Develop systematic methodology to alleviate design challenges, including synthesis, physical implementation, Timing/IREM sign-off, process what-if assessment, system performance evaluation, in advanced nodes or package  

2. Closely work with foundry and EDA vendors to define innovative HPC, Chiplet design methodologies 

3. Explore new circuit architecture, EDA features and define improvement direction from MTK product requirements

1 Develop the Timing/IR signoff criterion for leading process node and 3DIC.  

2 Maintain the Timing/IR signoff criterion ,provide issue solving and consultant for projects on abnormal/unfixable timing/IR violation  

3 Develop new Timing/IR signoff methodology to be applied during chip synthesis/APR/STA/IR .  

4 SPICE correlation for new timing/IR signoff criterion  

5 Regression test for every signoff methodology by STA violation/slack analysis, IR results  

6 Post-silicon data analysis for silicon-proven timing/IR signoff criterion

Role Summary: 

We are seeking a Principal Product Engineer to support advanced optical product development, NPI, manufacturing transfer, production ramp, and sustaining engineering in Taiwan. This is a senior individual contributor role requiring deep hands-on experience in fiber optics, optical module manufacturing, process integration, yield improvement, and cross-functional execution with engineering, operations, quality, supply chain, and contract manufacturing teams. 

The ideal candidate will serve as a technical lead for optical product engineering in Taiwan, helping drive products from development builds through qualification, pilot production, and high-volume manufacturing. 

Key Responsibilities: 

• Lead product engineering execution for optical products from prototype builds through qualification, production release, and sustaining support.  

• Support NPI planning, engineering builds, manufacturing readiness, test readiness, process transfer, and ramp execution.  

• Drive technical issue resolution across optical assembly, fiber attach, process integration, module test, final test, reliability, and customer quality.  

• Work closely with design engineering, optical engineering, packaging, test, reliability, operations, quality, and supply chain teams.  

• Partner with contract manufacturers and suppliers to resolve yield, quality, process, material, and production ramp issues.  

• Lead data-driven yield improvement using production data, failure pareto analysis, root-cause investigation, corrective action, and process optimization.  

• Support development and release of optical assembly and fiber attach processes, including process flows, control plans, inspection criteria, process windows, and manufacturing release criteria.  

• Provide technical leadership for product characterization, margin analysis, failure analysis, reliability learning, and production excursion response.  

• Help define manufacturing specifications, test limits, outgoing quality controls, and product-level production metrics.  

• Support customer or supplier technical escalations related to product quality, manufacturing performance, or reliability.

們正在尋找主動積極的「車用產品工程師」，負責監督晶圓製造流程、推動良率提升並解決生產與品質異常。您將與晶圓代工廠及內部跨部門團隊緊密合作，確保我們的車用 IC 產品符合嚴格的「零缺陷 (Zero Defect)」可靠度標準，並遵守相關車規法令規範。

• New product implementation, especially in Flip Chip related products​ 

• Assembly yield improvement, issue and RMA resolving​ 

• Package technology development and process improvement

1. 2.5D/3.5D package technology development​ 

2. SoC/Memory heterogeneous integration package development​ 

3. Package technology integration, NPI and MP​ 

4. Project management​

1. IC封裝/晶圓凸塊技術開發與管理  

2. 與封裝廠合作完成規劃之技術開發  

3. 先進封裝技術開發,品質驗證與生產良率管理  

4. 定期與不定期執行bumping/fan-out/WLCSP廠品質稽核

1. Conducting quality check procedures to ensure high-quality deliverables.​ 

2. Coordinating product quality issue to provide best-fit disposition for quality event impact material.​ 

3. Ensure lessons learned from prior projects are used to improve quality management process.​ 

4. Customer quality communication and RMA/FA management.

1. 先進製程技術製程開發  

2. 先進封裝技術開發

Develop advanced package technologies for MediaTek‘s HPC business

1. Develop systematic methodology to alleviate design challenges, including FIP development, synthesis, DFT, physical implementation, sign-off, process what-if assessment, system performance evaluation, in advanced nodes or package.  

2. Closely work with foundry and EDA vendors to define innovative HPC, Chiplet design methodologies. 

3. Explore new circuit architecture, EDA features and define improvement direction from MTK product requirements.

• 新產品導入量產 (IC 封裝部分) 

• 良率持續改善 

• 解決製程異常, 工程問題 

• 技術開發與製程改善

先進封裝技術開發 

1. 先進新產品導入技術開發 (新產片試產規劃, DRC/DRM檢驗, DOE及良率改善規劃, 量產區間及良率分析)  

2. 熟悉先進chiplet及3DIC封裝技術開發 

3. 晶圓級與面板級先進封裝結構設計

1. DFT architecture exploration & evaluation for next-gen process node & package technology of MediaTek: 

* Scan chain insertion & ATPG pattern generation 

* Pattern validation through simulation & silicon analysis(pass/fail, shmoo, fail log, etc.) 

* Diagnosis to help manufacture process improvement 

2. Co-work with SoC architect, RTL designer, physical design engineer, and package engineer to define best architecture for 3D-IC: 

* PPA(Performance/Power/Area) impact analysis & mitigation via DFT innovation 

* Develop & integrate DFT-related RTL design modules to test chip