CPU/GPU Design Verfication Engineer

1. 規劃量產測試以及量產functin pattern porting 

2. 測試以及驗證IC功能，性能，以及功耗等等相關測試 

3. 分析測試資料以及釐清相關測試的問題，並分析良率問題以及良率改善建議 

4. AVS low power的設計

於IC開發前/中/後期，開發IP及System level model。

1. Develop systematic algorithms to alleviate design challenges, including implementation, process what-if assessment, system performance evaluation, in advanced nodes or package 

2. Closely work with foundry and EDA vendors to define innovative HPC, Chiplet design methodologies 

3. Explore new EDA features and define improvement direction from MTK product requirements

1. 新產品開發討論 

2. 電源管理IC及電源管理單元晶片整合 

3. 與設計/生產/品保/軟體部門溝通協調 

4. 晶片開發滿足智慧手機, IOT, 車用, 以及ASIC的需求

1. 電源管理晶片架構與系統設計(手機/車用) 

2. 低功耗設計技術開發 

3. 混合訊號數位 IP 設計: voltage regulator, ADC, system clocking and start-up, TOP infra/bus, peripheral designs 

4. 電源管理晶片整合: front-end and back-end integration

1. 平台電源管理系統架構設計與規格定義, 包含功耗/溫度/性能等系統分析. 

2. 系統應用詳細電源需求與控制架構之分析與優化 

3. 電源管理芯片規格制定與新技術之開發.

1. DFT architecture exploration & evaluation for next-gen process node & package technology of MediaTek: 

* Scan chain insertion & ATPG pattern generation 

* Pattern validation through simulation & silicon analysis(pass/fail, shmoo, fail log, etc.) 

* Diagnosis to help manufacture process improvement 

2. Co-work with SoC architect, RTL designer, physical design engineer, and package engineer to define best architecture for 3D-IC: 

* PPA(Performance/Power/Area) impact analysis & mitigation via DFT innovation 

* Develop & integrate DFT-related RTL design modules to test chip

Work in Analog/Mixed-Signal Modeling and Verification Methodology Development group to establish, streamline and enhance new and existing AMS Behavioral Modeling related development method, coding and validation process and integration flows, and work hands-on with AMS IP Teams for AMS Behavioral Modeling flow and process experiments, demonstrations, adaptions, and deployment. The candidate will work with AMS IP teams including digital design, analog design, analog behavioral modeling and design verification members, apply and advance existing and evolving AMS Behavioral Modeling methodologies and processes, and contribute to establish and maintain Modeling Platform to ensure High Quality and High Efficiency of Pre-Si AMS Modeling, Validation and Verification delivery towards high quality silicon products. 

• Work in methodology development group to establish, streamline and enhance new and existing AMS Behavioral Modeling related development method, coding and validation process and integration flows. 

• Work with teams to enable deployment of new AMS Behavioral Modeling flow and processes through experiments, demonstrations, adaptions (for real projects in specified areas such as RF, etc) and integration.  

• Document on new flows and processes for AMS Behavioral Modeling. 

• Apply wide range of AMS Behavioral Modeling skills to help and support AMS IP or Chip Teams to establish or enhance new or existing Modeling capabilities, including but not limited to Model Development, Model Validation to ensure Consistency of Behavior with Original Circuit, Integration of Models into various Verification Environment, fixing Modeling issues found in simulation, etc.  

• Contribute to continuous improving on AMS Behavioral Modeling process for better quality and efficiency through methodology and process improvements.  

• Communicate and collaborate with global architecture, design, verification teams to address new needs or requirement on AMS Behavioral Modeling. 

Job Locations: 

• Taiwan:Hsinchu/Taipei 

• India: Bangalore 

• Singapore 

• USA:Santa Clara, CA/San Diego, CA

Work in Analog/Mixed-Signal Design Verification Methodology Development group to establish, streamline and enhance new and existing AMS DV related development method, coding process and integration flows, and work hands-on with AMS IP Teams for AMS DV flow and process experiments, demonstrations, adaptions, and deployment. The candidate will work with digital design, analog design, analog behavioral modeling and design verification teams, apply and advance existing and evolving Digital and AMS Verification methodologies and processes, and contribute to establish and maintain Verification Platform to ensure High Quality and High Efficiency of Pre-Si Verification Delivery towards high quality silicon products.  

• Work in methodology development team to establish, streamline and enhance new and existing AMS DV related development method, coding process and integration flows. 

• Work with teams to enable deployment of new flow and processes through experiments, demonstrations, adaptions (for real projects in specified areas such as SERDES, etc) and integration.  

• Document on new flows and processes for AMS DV. 

• Apply wide range of Digital and/or AMS DV skills to help and support AMS IP or Chip DV Teams to establish or enhance new or existing DV capabilities, including but not limited to developing scalable and portable Test bench, test cases, drivers, checkers, assertions and reference models, and running RTL and Gate Level simulations and reaching all coverage closures.  

• Contribute to continuous improving on AMS DV process for better quality and efficiency through methodology and process improvements.  

• Communicate and collaborate with global architecture, design, verification, and post-Silicon testing teams to address new needs or requirement on DV Support. 

Job Locations: 

• Taiwan:Hsinchu/Taipei 

• India: Bangalore 

• Singapore 

• USA:Santa Clara, CA/San Diego, CA

1. Work on 3~7nm design implementation, methodology, and sign-off 

2. Perform synthesis, DFT, floorplan, clock planning, place and route, timing closure, ECO, IR signoff, and physical verification 

3. Manage schedule, resolve design and flow issues, drive methodologies and execution

1. Develop scalable platform clocking architecture for automotive SoC 

2. Enhance SoC clock architecture and technology development to address the automotive SoC requirements 

3. Drive clock architecture and designs to optimize power, performance, and implementation, including physical design and timing closure

We are seeking skilled engineers for designing high-performance Virtualization and Interconnect Architecture and developing RTL for both Automotive and High-Performance Computing. 

Roles: 

1. Develop, assess, and refine RTL to achieve performance, power, area, and timing goals. 

2. Develop micro-architecture by exploring early high-level macro architectures, researching micro-architecture, and defining detailed specifications. 

3. Coordinate co-design efforts between architecture, software, and hardware teams to achieve functional realization. 

4. Develop and implement interconnect methodologies, such as simulation, emulation, implementation, and efficiency improvement.

1. Define power states and management hardware architecture for optimal power performance. 

2. Design microprocessor-based power management controller and HW assistance designs. 

3. Define power architecture by performing power rail tradeoff analysis with adaptive voltage scaling consideration

1.從系統應用功秏分析, 與 IP, SoC 與軟體團隊合作, 推進 SoC low power 軟硬體架構的演進. 

2.產品規格定義時, 分析不同架構與 IP 選項, 在系統應用功秏體驗的差異, 產出產品應用 power dash board, 提供產品規格決策的依據. 

3.執行或協助功秏量測, 與power model預估的功秏做校正 

4.分析PMIC/Power rail 設計, SoC power state 與 data-path power等, 並且提出SOC 設計優化方案 

5.提出系統優化的方向, 達到最佳的產品電池使用續航時間與使用體驗

- Logic/Physical Synthesis by using advanced optimization techniques(below N7) and generate optimized Gate Level Netlist for Timing, Area, Power. 

- Debug the timing/area/congestion issues and work with RTL & Physical designers to resolve them. 

- Run Formal Verification checks between RTL and Gate level netlist and debug the aborts, inconclusive and Logic Equivalency failures. 

- DFT insertion, ATPG and gate-level simulation 

- Developing Automation scripts and Methodology for all FE-tools including (Lint, CDC, RDC, Synthesis, STA, Power). 

- Interact with Physical Design Engineers and provide them with timing/congestion feedback.

協助電源管理晶片規格製定, 新 IP 開發規劃及產品驗證協助類比晶片IP開發, 驗證.

1. Work on 7nm~3nm design implementation, methodology, and sign-off 

2. Perform synthesis, DFT, floorplan, clock planning, place and route, timing closure, ECO, IR signoff, and physical verification 

3. Manage schedule, resolve design and flow issues, drive methodologies and execution

開發手機/平板SoC模擬及分析平台， 

從系統效能，功率消耗，溫度控制...等多重面向分析產品競爭力， 

進而從系統角度優化硬體架構及軟體控制策略。

* Define and optimize SOC hardware architecture and associated software flows in aspects of system performance/power/area to improve MediaTek‘s product competitiveness. 

* Develop simulation and analysis platforms for performance/power/area analysis. 

* Work Loction : HsinChu, Taipei

1. Work on 7nm~3nm design implementation, methodology, and sign-off 

2. Perform synthesis, DFT, floorplan, clock planning, place and route, timing closure, ECO, IR signoff, and physical verification 

3. Manage schedule, resolve design and flow issues, drive methodologies and execution