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  • 類比電路設計工程師(Data Converter)

    新竹市東區|面議(經常性薪資4萬/月含以上)
    面議(經常性薪資4萬/月含以上)|2年工作經驗以上|碩士、博士|千大企業高薪100

    Analog/Mixed-signal circuit design


    要求條件
    • 電機工程學類,電子工程學類 相關科系
    展開收合
    2026-04-07
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  • IO Circuit Design Engineer

    新竹市東區|面議(經常性薪資4萬/月含以上)
    面議(經常性薪資4萬/月含以上)|4年工作經驗以上|碩士、博士|千大企業高薪100

    28nm及以下先進製程(含FinFET) IO電路和ESD防護設計, 工作內容包含  

    (1) GPIO電路設計(包含ESD/LU防護) 

    (2) 特殊應用IO (SD3.0/SIM card/eMMC等)電路設計(包含ESD/L防護)  

    (3) 高速IO和特殊應用IO在事業部專案上展開和執行 

     

    - Advance node (28nm and beyond, including FetFET) IO circuitry and ESD protection design covering fields for  

    (a) General purpose IO circuit design (with ESD/LU protection)  

    (b) Specialty IO (SD3.0/SIM card/eMMC etc.) circuit design (with ESD/LU protection)  

    (c) Project related implementation for high speed/specialty IO Interface - High speed IO, specialty IO circuit design, ESD protection circuit design and simulation.  

     

    Work with project leader, layout, packaging and system engineers to meet design and system specifications.  

    Work with IO library modeling, characterization teams closely for IP release.


    要求條件
    • 物理學類,通信學類,電機工程學類 相關科系
    展開收合
    2026-04-07
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  • FR1天線系統設計工程師

    新竹市東區|面議(經常性薪資4萬/月含以上)
    面議(經常性薪資4萬/月含以上)|2年工作經驗以上|碩士、博士|千大企業高薪100

    1. FR-1 平台天線解決方案開發與驗證 

     

    2. 使用EM模擬軟體進行天線解決方案性能評估 

     

    3. 與跨部門團隊合作開發新MTK平台天線解決方案


    要求條件
    • 電機工程學類,電子工程學類,通信學類 相關科系
    展開收合
    2026-04-07
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  • 資深電源管理系統架構工程師

    新竹市東區|面議(經常性薪資4萬/月含以上)
    面議(經常性薪資4萬/月含以上)|6年工作經驗以上|碩士|千大企業高薪100

    1. 平台電源管理系統架構設計與規格定義, 包含功耗/溫度/性能等系統分析. 

    2. 系統應用詳細電源需求與控制架構之分析與優化 

    3. 電源管理芯片規格制定與新技術之開發.

    展開收合
    2026-04-07
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  • 電源管理系統應用工程師

    新竹市東區|面議(經常性薪資4萬/月含以上)
    面議(經常性薪資4萬/月含以上)|2年工作經驗以上|碩士、博士|千大企業高薪100

    1. 系統應用電源需求與控制架構分析 

    2. 電源管理晶片規格制定與驗證 

    3. 類比電路開發與驗證 

    4. 驗證電路板設計 

    5. 自動化測試開發

    展開收合
    2026-04-07
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  • Analog/Mixed-Signal Modeling Methodology Development Engineer

    新竹市東區|面議(經常性薪資4萬/月含以上)
    面議(經常性薪資4萬/月含以上)|10年工作經驗以上|大學、碩士|千大企業高薪100

    Work in Analog/Mixed-Signal Modeling and Verification Methodology Development group to establish, streamline and enhance new and existing AMS Behavioral Modeling related development method, coding and validation process and integration flows, and work hands-on with AMS IP Teams for AMS Behavioral Modeling flow and process experiments, demonstrations, adaptions, and deployment. The candidate will work with AMS IP teams including digital design, analog design, analog behavioral modeling and design verification members, apply and advance existing and evolving AMS Behavioral Modeling methodologies and processes, and contribute to establish and maintain Modeling Platform to ensure High Quality and High Efficiency of Pre-Si AMS Modeling, Validation and Verification delivery towards high quality silicon products. 

    • Work in methodology development group to establish, streamline and enhance new and existing AMS Behavioral Modeling related development method, coding and validation process and integration flows. 

    • Work with teams to enable deployment of new AMS Behavioral Modeling flow and processes through experiments, demonstrations, adaptions (for real projects in specified areas such as RF, etc) and integration.  

    • Document on new flows and processes for AMS Behavioral Modeling. 

    • Apply wide range of AMS Behavioral Modeling skills to help and support AMS IP or Chip Teams to establish or enhance new or existing Modeling capabilities, including but not limited to Model Development, Model Validation to ensure Consistency of Behavior with Original Circuit, Integration of Models into various Verification Environment, fixing Modeling issues found in simulation, etc.  

    • Contribute to continuous improving on AMS Behavioral Modeling process for better quality and efficiency through methodology and process improvements.  

    • Communicate and collaborate with global architecture, design, verification teams to address new needs or requirement on AMS Behavioral Modeling. 

    Job Locations: 

    • Taiwan:Hsinchu/Taipei 

    • India: Bangalore 

    • Singapore 

    • USA:Santa Clara, CA/San Diego, CA

    展開收合
    2026-04-07
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  • Analog/Mixed-Signal Design Verification Methodology Development Engineer

    新竹市東區|面議(經常性薪資4萬/月含以上)
    面議(經常性薪資4萬/月含以上)|10年工作經驗以上|大學、碩士|千大企業高薪100

    Work in Analog/Mixed-Signal Design Verification Methodology Development group to establish, streamline and enhance new and existing AMS DV related development method, coding process and integration flows, and work hands-on with AMS IP Teams for AMS DV flow and process experiments, demonstrations, adaptions, and deployment. The candidate will work with digital design, analog design, analog behavioral modeling and design verification teams, apply and advance existing and evolving Digital and AMS Verification methodologies and processes, and contribute to establish and maintain Verification Platform to ensure High Quality and High Efficiency of Pre-Si Verification Delivery towards high quality silicon products.  

    • Work in methodology development team to establish, streamline and enhance new and existing AMS DV related development method, coding process and integration flows. 

    • Work with teams to enable deployment of new flow and processes through experiments, demonstrations, adaptions (for real projects in specified areas such as SERDES, etc) and integration.  

    • Document on new flows and processes for AMS DV. 

    • Apply wide range of Digital and/or AMS DV skills to help and support AMS IP or Chip DV Teams to establish or enhance new or existing DV capabilities, including but not limited to developing scalable and portable Test bench, test cases, drivers, checkers, assertions and reference models, and running RTL and Gate Level simulations and reaching all coverage closures.  

    • Contribute to continuous improving on AMS DV process for better quality and efficiency through methodology and process improvements.  

    • Communicate and collaborate with global architecture, design, verification, and post-Silicon testing teams to address new needs or requirement on DV Support. 

    Job Locations: 

    • Taiwan:Hsinchu/Taipei 

    • India: Bangalore 

    • Singapore 

    • USA:Santa Clara, CA/San Diego, CA

    展開收合
    2026-04-07
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  • 4G/5G 通訊協定與系統工程師

    新竹市東區|面議(經常性薪資4萬/月含以上)
    面議(經常性薪資4萬/月含以上)|2年工作經驗以上|碩士、博士|千大企業高薪100

    • 此職位屬於聯發科技modem客戶工程團隊,該團隊任務為與內部研發團隊合作,支援全球一流智能手機客戶的無線通訊技術(包括LTE、5G Sub-6GHz和5G mmWave技術)。 

    • 此職位主要職責在與客戶合作過程中帶領技術討論,並與內外部不同團隊合作,共同討論並解決客戶問題、滿足需求。 

    • 此職位需具備深入研究技術問題、了解客戶需求分析與功能開發的能力及良好應變能力。 

     

    • This is an exciting role in the MediaTek wireless technology group within the modem customer engineering team working with internal R&D team and support tier-1 global smartphone customers in wireless technologies (LTE, 5G Sub-6GHz, and 5G mmWave technologies)  

    • You will play a key technical role in working with internal and external stakeholders to lead technical discussion and drive customer issues to resolution.  

    • This is a dynamic position that will interact and collaborate with different teams and site location.  

    • Ability to deep dive technical issues, understand customer requirement analysis and feature development. Looking for 4G/5G Modem Protocol / System Engineer with technical breadth in the protocol stack.


    要求條件
    • 電機工程學類,電子工程學類,通信學類 相關科系
    展開收合
    2026-04-07
    收藏職缺
    我要應徵
  • 5G測試平台Linux性能優化工程師

    新竹市東區|面議(經常性薪資4萬/月含以上)
    面議(經常性薪資4萬/月含以上)|4年工作經驗以上|碩士、博士|千大企業高薪100

    分析及優化手機 5G TestBed 平台的效能,包括以下項目 

    1. 整合與移植不同 Linux 平台 (Ex. Ubuntu, Cent, RedHat, ...) 

    2. 整合與應用 Intel/AMD CPU Accelerator API (Ex. Intel Core i9 9/10/12th AVX/TBB/MKL; AMD...) 

    3. 分析與調校系統整體效能 (Ex. Linux Kernel, Process, Thread, Peripheral(Ethernet/PCIe/...) Driver, ...)

    展開收合
    2026-04-07
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  • Embedded Memory IP Designer

    新竹市東區|面議(經常性薪資4萬/月含以上)
    面議(經常性薪資4萬/月含以上)|5年工作經驗以上|碩士|千大企業高薪100

    This position involves developing memory architectures, creating circuit implementation techniques and be an interface with CAD team for full verification and model generation. You have opportunity to know how memory design can be implemented into all Mediatek products.

    展開收合
    2026-04-07
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  • 類比 SerDes/PLL 電路設計工程師

    新竹市東區|面議(經常性薪資4萬/月含以上)
    面議(經常性薪資4萬/月含以上)|經驗不拘|碩士|千大企業高薪100

    高速類比 SerDes 電路設計 

    Work Location : 新竹/竹北/台北/台南

    展開收合
    2026-04-07
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  • 電源管理IC應用工程師

    新竹市東區|面議(經常性薪資4萬/月含以上)
    面議(經常性薪資4萬/月含以上)|2年工作經驗以上|碩士、博士|千大企業高薪100

    協助電源管理晶片規格製定, 新 IP 開發規劃及產品驗證協助類比晶片IP開發, 驗證.

    展開收合
    2026-04-07
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  • 電源管理IC設計工程師_新竹

    新竹市東區|面議(經常性薪資4萬/月含以上)
    面議(經常性薪資4萬/月含以上)|2年工作經驗以上|碩士|千大企業高薪100

    MTK電源管理部門設計設計電源管理IC及電源管理單元以滿足各式各樣智慧手機, IOT, 車用, 以及ASIC的需求. 

    職缺包含:  

    1. DC-DC 轉換器 

    2. 線性電壓調節器 

    3. 切換電壓調節器

    展開收合
    2026-04-07
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