【預聘】實習工程師

Please apply for this position on NXP official website: https://pse.is/836k2a 

Job Responsibilities: 

APAC Central Competence Team works with external foundries to ensure stable chip supply for business lines across NXP.  

The primary responsibility of this role is to locally drive the lead products ramp up under new technology introduction (NTI). 

The key areas of responsibility of the jobholder are: 

1. Close collaboration with foundries, NXP technology groups, the business lines and various other stakeholders to qualify and release process 

2. Front end process safe launch owner. Closely work with foundries at ramp up phase and drive for manufacturability and yield improvement. 

3. Interface with key customers on critical projects. 

4. Lead and steer the projects towards timely completion to support NXP business needs 

5. Main decision maker on subjects related to process integration, striking a good balance between the various dynamics in a project; not limiting to technical judgement, resource planning, project schedule, logistics, supplier relationships etc 

Requirements / preferences: 

1. Bachelor or MSc in physics or electrical engineering. 

2. ＞10 years of experience with front-end IC process integration, working in foundries’ production or development teams 

3. In-depth knowledge of IC devices and processes. FinFET and NVM knowledge is a plus. 

4. Strong understanding of yield enhancement techniques and data analysis 

5. Must be fluent in English and Mandarin 

6. Hands on experience in being a lead; leading teams with responsibilities in development / transfer projects or production ramp up. 

7. Good communication skills. Having the ability to influence and steer a discussion 

8. Pro-active working attitude, creative, pragmatic, enterprising and result driven. 

9. Familiar in managing/working with foundries, maximizing leverage from foundries

The key areas of responsibility of the jobholder are: 

- Collaborate closely with foundries, NXP technology teams, and business lines to qualify and release advanced FinFET processes. 

- Provide technical leadership in semiconductor device physics, especially in FinFET architecture and behavior. 

- Interface with internal and external stakeholders on critical development and transfer projects. 

- Lead and steer projects to meet timelines and business objectives. 

- Make key decisions on process integration, balancing technical, logistical, and strategic factors. 

- Support NTI process transfers within foundries and NXP joint ventures 

Requirements / preferences:  

- Bachelor‘s or Master‘s degree in Electrical Engineering, Physics, or related field. 

- Minimum 10 years of experience in semiconductor device engineering, with a strong focus on advanced logic/RF devices. 

- Proven hands-on experience with HKMG and FinFET technologies in production or development environments. 

- Deep understanding of semiconductor device physics, especially HKMG and FinFET. 

- Strong analytical skills in yield enhancement and electrical data analysis. 

- Fluent in English and Mandarin. 

- Demonstrated leadership in development, transfer, or ramp-up projects. 

- Excellent communication and influencing skills. 

- Proactive, pragmatic, and results-driven mindset. 

- Experience working with foundries and leveraging external manufacturing capabilities .

***Please apply for this position on NXP official website: https://pse.is/8ms2kr 

Role Purpose 

Lead the development and optimization of high-voltage (HV) and BCD device architectures. This role requires a deep understanding of device physics and a data-driven approach to ensure industry-leading performance and reliability for power management solutions. 

Key Responsibilities 

－ Device Development: Lead the architecture design and optimization of HV devices (LDMOS, EDMOS, ESD) on 180nm to 55nm BCD nodes. 

－ Physics Analysis: Analyze and optimize Device Physics parameters, including BV, Rdson, SOA, and reliability (HCI/NBTI). 

－ Simulation & Modeling: Utilize TCAD for 2D/3D process and device simulations to accelerate development cycles. 

－ Device Verification: Define verification plans and execute statistical analysis using JMP for DOE and WAT data. 

－ Design Integration: Work within Cadence environments for layout review and test structure design. 

－ Cross-functional Collaboration: Partner with PI and PE teams to resolve yield, reliability, and manufacturing bottlenecks. 

Required Qualifications 

－ Experience: Master‘s or Ph.D. in EE, Physics, or related field with 10+ years of semiconductor industry experience. 

－ Technical Expertise: 

1. Profound knowledge of Device Architecture and Device Physics. 

2. Hands-on experience in 180nm to 55nm BCD process nodes. 

－ Tools: 

1. Expertise in TCAD (Sentaurus / Silvaco). 

2. Expertise in JMP for statistical data analysis. 

3. Proficiency in Cadence (Layout/Virtuoso). 

Preferred Qualifications (Plus) 

－ Advanced Power Devices: Experience with GaN, SiC, or IGBT development. 

－ Silicon Photonics: Knowledge of Photonics integration and device physics. 

－ Domain Knowledge: 

1. Process Integration (PI): Understanding of mask flow and doping profiles. 

2. Product Engineering (PE): Experience in CP/FT data correlation and yield enhancement. 

Competencies 

－ Accountability: Strong ownership of project milestones and outcomes. 

－ Critical Thinking: Ability to identify root causes in complex device failures. 

－ Interpersonal Skills: Effective communication across design and foundry teams. 

－ Data-driven: Committed to objective decision-making through rigorous data analysis.

Role Summary:  

The NVM Reliability team is responsible for characterizing, modeling, and enabling next-generation Non-Volatile Memory technologies, enabling new product creation company-wide. 

Job Responsibility:  

－Interface with foundries and other external suppliers of technology and IP to assess reliability margin to product applications.  

－Establish qualification requirements for new technology and product introduction.  

－Perform rigorous statistical analysis of reliability characterization data. 

－Enable high reliability during volume production by working with product groups to address risk areas. 

－Support business groups with customer requests for technical information, including reliability characterization results, risks assessments, and consultation on issues. 

－Communicate study conclusions and recommendations to internal and external teams.  

Job Qualification:  

－Bachelor‘s, Masters, or Doctoral degree in Electrical Engineering, Applied Physics, or equivalent, with 10 years of industry experience. 

－Experienced in data processing and analysis (e.g. Python, JMP, Matlab, Exensio). 

－Software development experience, such as familiarity with microcontroller software development (C/C++) is desired. 

－Interest in statistics and solid-state device fundamentals, especially as applied to emerging non-volatile memory technologies like MRAM and RRAM.  

－Must be curious, proactive, and detail-oriented. 

－Able to work in a team environment, communicate effectively in English and Mandarin, and solve problems.

工作項目： 

先進製程元件工程、可靠度分析與驗證、製程平台整合與管理 

應徵條件： 

1. 具6年以上先進製程整合/元件技術/元件可靠度知識與可靠度驗證經驗之相關經驗者 (以上具任一專長即可) 

2. 有HKMG/FinFET/Nanosheet先進製程相關經驗者尤佳 

3. 碩士以上，電機、電子、物理、光電、材料、化學等相關科系畢業者尤佳

工作項目： 

1. 負責wifi產品的yield maintain & improvement 

2. 負責新進製程的量產導入以及轉廠評估 

3. Co-work with Foundry for CP yield improvement 

4. Co-work with SD/TE for FT yield improvement. 

5. 支援RMA案件的相關分析 

應徵條件： 

1. 熟悉半導體元件物理. 

2. 熟悉相關邏輯製程參數, WAT analysis,process flow 

3. 熟悉量產業務.(tape out, Job view, WAT analysis, Reliability calculation, OLT, yield analysis, RMA) 

4. 有先進製程(12nm 以下FINFET製程)量產經驗者尤佳 

5. 有車用電子相關經驗者尤佳 

6. 良好的人際關係以及跨部門溝通能力

1.蝕刻先進製程開發,熟悉實驗流程(實驗、評價解析、方案報告) 

2.協同客戶導入新裝置製程及新技術開發。 

3.維持現有Process Of Record及Trouble-shooting解決問題的能力。 

4.具良好溝通能力,理解客戶需求及跨部門有效溝通。

1.新技術與結構研發 

2.晶圓整合結構開發 

3.整合流程設計 

4.實驗設計 

5.物性與電性測試分析

1.製程整合與優化 

2.新製程導入與驗證 

3.資料分析與報告

【工作內容】 

1.新機型評價與推廣。 

2.新製程技術評價與推廣。 

3.客戶端現場異常處理。 

4.其他主管交辨事項。 

【其他條件】 

※TOEIC 450以上。 

※需配合值班。 

※自備汽車尤佳(另有每月車輛津貼及交通費補助)。 

※錄取後需先至新竹湖口工廠教育訓練。

1. 產品測試資料報告整理 

2. 產品 FAILURE 分析 

3. 製程改善分析

工作內容: 

1.新產品開發缺陷分析 

2.製程異常分析與改善 

3.新製程實驗評估 

4.班別:常日班、需假日/小夜輪值

1.邏輯元件製程開發 

2.整合製程 

3.良率提升 

4.光罩設計

1.邏輯元件開發 (LV/ SRAM device design and development)  

2.元件開發工作 (EDR, SPICE, Reliability, Testkey design, WAT analysis, Device characteristics) 

3.良率與製程相關性分析 (Yield & process correlation analysis)

1. DRAM research and layout design/ tape out. 

2. DRAM process flow setup and optimize. 

3. DRAM architecture & characteristic development for advance generation 

4. DRAM process tuning(co-work with module) and improvement

1. 客戶與公司內部單位的溝通橋樑 

2. 負責處理客戶產品pre-tapeout, tape-out, pilot run到mass production的相關事務

1. 產品異常處理：解決線上製程問題，協助新製程導入與技術移轉。 

2. 製程良率改善及生產成本降低之專案。

1. Discrete Device 

2. Power MOSFET 

3. TSV, IGBT 

4. 常日班，需配合假日值班

1. To manage Fab‘s reliability activities e.g. process reliability qual, PCN qual and reliability monitor (WLR monthly, conformance test quarterly) 

2. To coordinate projects & control reliability qual status with good communication skill to co-work with TD/PEI , PKG/Testing and RE. 

3. To meet customer‘s reliability related expectation (CSR)

1.RF/mm-wave Device Characterization; Measurement, Data Analysis and Reporting. 

2.Device pcell design, test structure creation and tape out. 

3.Work with modeling & PDK team for design enablement, model validation and pcell improvement. 

4.Liaise with vendor, assist lab manager for measurement tool set up, calibration, maintain good measurement quality.