資深基板佈線工程師

高速類比SerDes電路全客製化佈局設計及自動化流程設計 

Fully custom layout design for analog high-speed SerDes circuit and layout automation flow development.

類比、射頻、3D-IC矽中介層等電路全客製化佈局設計及自動化流程設計

1. New SBT vendor bring up , New SBT vendor YIP , troubleshooting and Ops ​ 

2. 3D, 3.5D & e-IVR Technology Enabling, CPC/CPO technology building block development​ 

3. Common strip format unification management ​ 

4. Advanced PCB Ultra-Large size. I.e., CoWoP, DCAI PCB w/ high layer counts (PCB vendor ISU, GCE, UMTC, VGT ) ​ 

5. PCB technology development and DRM owner

1. Serdes PMA IP architecture planning 

2. Serdes PMA IP RTL coding 

3. Serdes PMA IP front-end and back-end integration 

4. Co-work with PCS and MAC design team and DV team for IP verification 

5. Co-work with Analog design team for PHY co-simulation 

6. Co-work with Algorithm team for algorithm implementation and bit-true verification

1. DFT architecture exploration & evaluation for next-gen process node & package technology of MediaTek: 

* Scan chain insertion & ATPG pattern generation 

* Pattern validation through simulation & silicon analysis(pass/fail, shmoo, fail log, etc.) 

* Diagnosis to help manufacture process improvement 

2. Co-work with SoC architect, RTL designer, physical design engineer, and package engineer to define best architecture for 3D-IC: 

* PPA(Performance/Power/Area) impact analysis & mitigation via DFT innovation 

* Develop & integrate DFT-related RTL design modules to test chip

28nm及以下先進製程(含FinFET) IO電路和ESD防護設計, 工作內容包含  

(1) GPIO電路設計(包含ESD/LU防護) 

(2) 特殊應用IO (SD3.0/SIM card/eMMC等)電路設計(包含ESD/L防護)  

(3) 高速IO和特殊應用IO在事業部專案上展開和執行 

- Advance node (28nm and beyond, including FetFET) IO circuitry and ESD protection design covering fields for  

(a) General purpose IO circuit design (with ESD/LU protection)  

(b) Specialty IO (SD3.0/SIM card/eMMC etc.) circuit design (with ESD/LU protection)  

(c) Project related implementation for high speed/specialty IO Interface - High speed IO, specialty IO circuit design, ESD protection circuit design and simulation.  

Work with project leader, layout, packaging and system engineers to meet design and system specifications.  

Work with IO library modeling, characterization teams closely for IP release.