可測試設計 (DFT) 工程師 / 資深工程師(台南)

工作項目： 

1. CPU & GPU Backend Implementation (APR) 

2. CPU/GPU Backend Flow Development, Enhancement & Automation 

3. Advanced CPU/GPU Technology Development: High-performance, Low Power, and PPA Optimization 

應徵條件： 

1. 碩士以上；電機、資工、電子相關科系畢業為主。 

2. 熟悉 APR Tools (Innovus、ICC2、Fusion Compiler…)，有Synthesis、STA/IR Analysis、Physical Verification等相關經驗者佳。 

3. 具備程式設計能力，熟悉 TCL/Perl/C++/Python。 

4. 有 High Performance CPU/GPU APR經驗尤佳。 

5. 個性積極負責、勇於迎接新挑戰，對於 High-Performance CPU/GPU Technology 有興趣者。

工作項目： 

1.High-Performance CPU & GPU & Armv9 & Server-class Compute SubSystem (CSS) Frontend Implementation (including STD cells/SRAM analysis & selection, DFT insertion, Synthesis, low power cells insertion & verification) 

2.Advanced ASIC Implementation Flow Development & Automation: High-performance, Low Power, and PPA (Performance, Power, Area) Optimization  

3.Physical Synthesis and Collaboration with P&R in Timing/Congestion Analysis and PPA Optimization  

4.Perform Power Replay and Power Analysis 

5.Perform Pre-layout/Post-layout Quality Checks (including LEC, CLP, ATPG, GCA, PPA quality) 

應徵條件： 

1.碩士以上；電機、電機與控制、資訊工程、電子相關科系畢業為主。 

2.熟悉 Frontend EDA Tools、Synthesis、Timing Analysis、Low Power Implementation Flow & PPA (Performance, Power, Area) Optimization。 

3.有開發Automation Flow的經驗，熟悉 TCL/Perl/Python。 

4.英文能力良好，聽說讀寫精通。 

5.有 CPU、GPU、Multi-Core Processor、Compute SubSystem Implementation 經驗尤佳，例如 Synthesis/Floorplan/CLP/DFT等。 

6.積極負責、勇於迎接挑戰，對於 High-Performance CPU/GPU/CSS、Advanced PPA Optimization、Energy Efficiency Technology 有興趣者。

工作項目： 

1. ARM Architecture based Complex CPU Subsystem Platform Design & Integration, Add-on Features Enablement and IP Development 

2. SoC Architecture Exploration, Performance Projection and Bottleneck Analysis 

3. Benchmark/Power Characterization on Emulation Platform, Result Analysis and Optimization 

4. CPU Architecture/Micro-architecture Research 

5. Involvement of Post-silicon Bring-up and Debug 

應徵條件： 

1.碩士以上；電機、資工、電子相關科系畢業為主。 

2.具IP開發經驗，熟悉 SoC Integration & Design Flow、Frontend Timing/Power Analysis EDA Tools。 

3.熟悉ARMv7/v8-A CPU 架構及AMBA protocol，有 ARM Cortex-A CPU/Subsystem Design/Integration/PPA Optimization/Sign-off 經驗尤佳。 

4.具Emulation platform (Zebu, Palladium)經驗尤佳。 

5.有 Low Power Design & Verification、Post-Silicon Validation & Debug 經驗尤佳。 

6.積極負責、溝通協調能力強、勇於迎接挑戰，對於 High-Performance CPU Technology 有興趣者。

工作項目： 

1. 開發維護 in-house VIP 

2. 支援產品線 IC 驗證計劃 

工作地點：台南科學園區 

應徵條件： 

1. 大學、碩士以上；電機、電機與控制、資訊科學、自動控制、通訊工程、電信、資訊工程、電子、動力機械相關科系畢業為主。 

2. 熟悉 SystemVerilog 驗證語言和 perl 相關 scripts。 

3. 熟悉 UVM 或 VMM methodology 。 

4. 熟悉 PCIE/USB/SATA 等 protocol 。 

5. 具4年以上 IC 驗證相關經驗。 

6. 有 VIP 開發經驗者尤佳。