數位IC驗證工程師R1

工作項目： 

1. High-Performance CPU/GPU Timing & Power Integrity Signoff  

2. High-Performance CPU/GPU Post-Silicon Validation & Debug, Sim-to-Silicon Correlation 

3. 協同開發 CPU/GPU Advanced DFT, On-Chip PVT Sensor, Performance Improvement & Power Management 等先進技術 

4. 支援產品 SoC Projects，協同執行 High-Performance CPU/GPU 專案開發，導入先進 IP 及技術 

應徵條件： 

1. 碩士以上；電機、資工、電子相關科系畢業為主。 

2. 熟悉 SoC Integration & Design Flow、Frontend/Backend/DFT/Timing/IR Drop/Power Analysis EDA Tools。 

3. 有 ARM Cortex-A CPU/Subsystem Design/Integration/PPA Optimization/Sign-off 經驗尤佳。 

4. 有 Chip-Level, Package & PCB Power Integrity Optimization 經驗尤佳。 

5. 有On-Chip PVT Sensor 開發經驗尤佳。 

6. 有Post-Silicon Validation, Debug 及 RMA 分析經驗尤佳。 

7. 積極負責、溝通協調能力強、勇於迎接挑戰，對於 High-Performance CPU/GPU Technology 有興趣者。

工作項目： 

1. CPU & GPU Backend Implementation (APR) 

2. CPU/GPU Backend Flow Development, Enhancement & Automation 

3. Advanced CPU/GPU Technology Development: High-performance, Low Power, and PPA Optimization 

應徵條件： 

1. 碩士以上；電機、資工、電子相關科系畢業為主。 

2. 熟悉 APR Tools (Innovus、ICC2、Fusion Compiler…)，有Synthesis、STA/IR Analysis、Physical Verification等相關經驗者佳。 

3. 具備程式設計能力，熟悉 TCL/Perl/C++/Python。 

4. 有 High Performance CPU/GPU APR經驗尤佳。 

5. 個性積極負責、勇於迎接新挑戰，對於 High-Performance CPU/GPU Technology 有興趣者。

工作項目： 

1.High-Performance CPU & GPU & Armv9 & Server-class Compute SubSystem (CSS) Frontend Implementation (including STD cells/SRAM analysis & selection, DFT insertion, Synthesis, low power cells insertion & verification) 

2.Advanced ASIC Implementation Flow Development & Automation: High-performance, Low Power, and PPA (Performance, Power, Area) Optimization  

3.Physical Synthesis and Collaboration with P&R in Timing/Congestion Analysis and PPA Optimization  

4.Perform Power Replay and Power Analysis 

5.Perform Pre-layout/Post-layout Quality Checks (including LEC, CLP, ATPG, GCA, PPA quality) 

應徵條件： 

1.碩士以上；電機、電機與控制、資訊工程、電子相關科系畢業為主。 

2.熟悉 Frontend EDA Tools、Synthesis、Timing Analysis、Low Power Implementation Flow & PPA (Performance, Power, Area) Optimization。 

3.有開發Automation Flow的經驗，熟悉 TCL/Perl/Python。 

4.英文能力良好，聽說讀寫精通。 

5.有 CPU、GPU、Multi-Core Processor、Compute SubSystem Implementation 經驗尤佳，例如 Synthesis/Floorplan/CLP/DFT等。 

6.積極負責、勇於迎接挑戰，對於 High-Performance CPU/GPU/CSS、Advanced PPA Optimization、Energy Efficiency Technology 有興趣者。

應徵條件： 

1. 碩士以上；電機、電機與控制、資訊工程、電子相關科系畢業為主。 

2. 熟悉 Verilog RTL Design、SoC Integration & Design Flow、Frontend EDA Tools、Synthesis & STA Methodology、Low Power Design & Verification。 

3. 具備 IP Integration、Hierarchical Implementation、Verification 能力；熟悉 TCL/Perl/C++/Python。 

4. 英文能力良好，聽說讀寫精通。 

5. 有 CPU、GPU、Multi-Core Processor Development 經驗尤佳，例如 Design/Integration/Synthesis/DFT/Timing Closure/Sign-off/Production 等。 

6. 積極負責、勇於迎接挑戰，對於 High-Performance CPU/GPU、Advanced PPA Optimization、Energy Efficiency Technology 有興趣者。 

工作項目： 

1. High-Performance CPU & GPU Frontend Implementation 

2. Advanced CPU Technology Development: High-performance, Ultra-low Power, and PPA Optimization 

3. Processor Frontend Development Flow Enhancement & Automation 

應徵條件： 

1. 碩士以上；電機、電機與控制、資訊工程、電子相關科系畢業為主。 

2. 熟悉 Verilog RTL Design、SoC Integration & Design Flow、Frontend EDA Tools、Synthesis & STA Methodology、Low Power Design & Verification。 

3. 具備 IP Integration、Hierarchical Implementation、Verification 能力；熟悉 TCL/Perl/C++/Python。 

4. 英文能力良好，聽說讀寫精通。 

5. 有 CPU、GPU、Multi-Core Processor Development 經驗尤佳，例如 Design/Integration/Synthesis/DFT/Timing Closure/Sign-off/Production 等。 

6. 積極負責、勇於迎接挑戰，對於 High-Performance CPU/GPU、Advanced PPA Optimization、Energy Efficiency Technology 有興趣者。

工作項目： 

Design block integration / clcok-gen structure design / synthesis / timing analysis / LEC / scan-insert. 

應徵條件： 

1. 碩士以上; 電機工程、電信工程、電子工程、資訊科學等相關科系畢業為主。 

2. 具2年以上 SoC整合或 synthesis/sta等相關經驗者為佳。

工作項目： 

1. Data bus controller. 

2. 影像處理。 

3. 影像壓縮。 

4. IP整合。 

應徵條件： 

1. 碩士以上; 電機工程、電信工程、電控工程、電子工程、資訊工程、通訊工程相關科系畢業為主。 

2. 具1年以上相關經驗者為佳。 

3. 具備以下任一工程能力： 

(1) 參與過 data bus access/arbitration相關控制電路設計。 

(2) 參與過影像處理相關控制電路設計，並具備相關演算法有一定基礎知識。 

(3) 具備優化電路設計能力，以及實際參與電路量產/除錯經驗。 

(4) 具有IC整合工作經驗者尤佳。

工作項目： 

Verification for High Speed PHY projects, which includes: 

1. Responsibility for test plans, testbench documentation and implementation. 

2. Use SystemVerilog language, SVA and UVM methodology for block level verification. 

3. Debug tests with design engineers to deliver functionally correct design blocks. 

4. Close coverage measures to identify verification holes and show progress towards tape-out. 

5. Write scripts to automate routine parts of verification workflow. 

應徵條件： 

1. 碩士以上; 電子、電機、資工、電信、電控、資科等相關科系畢業為主。 

2. 具0~3年下列經驗之一者尤佳： 

(1) Experience verifying digital logic at RTL using SystemVerilog for FPGAs and/or ASICs. 

(2) Experience verifying digital systems using standard IP components/interconnects. 

(3) Experience creating and using verification components and environments in standard verification methodology. 

3. Preferred qualifications: 

(1) Experience with high speed MAC/PHY RTL design or verification. 

(2) Experience with UVM methodology and coding. 

(3) Good English verbal communication skills.

工作項目： 

Microprocessor design. Desired skills and experience includes: 

1. Knowledge of DSP, microprocessor and computer architecture fundamentals. 

2. Experience in RTL design and ability to make trade-offs between power, performance and area appropriately. 

3. Experience in the microprocessor design cycle: initial concept, micro-architecture, implementation, verification, documentation and support. 

應徵條件： 

1. 碩士以上; 電子、電機、資工、電信、電控、資科等相關科系畢業為主。 

2. 具相關工作經驗者尤佳。

工作項目： 

1. 研發/導入Emulation/Prototyping技術。 

2. Emulation Performance Optimization. 

3. Validation Flow Optimization. 

4. 自動化程式開發。 

應徵條件： 

1. 碩士; 電機工程、資訊工程相關科系畢業為主; 兩科系/領域都有學歷者佳。 

2. 熟悉 Synopsys Zebu/HAPS or Cadence Palladium/Protium者佳。 

3. 熟悉 IC Validation Flow or Software Bring Up Flow者佳。 

4. 熟悉自動化 script語言(Ex: Python)者佳。

工作項目： 

1. 建立IC設計後段驗證流程，並撰寫自動化程式。 

2. 建立並維護DRC/LVS/SVS/LVL/ERC/PERC相關檔案及流程。 

3. 分析並解決PV相關問題。 

應徵條件： 

1. 碩士以上；電機、電機與控制、電信、電子、資工、資訊相關科系畢業為佳。 

2. 無經驗可；具相關工作經驗者佳。 

3. 熟悉 Linux工作環境以及 TCL/shell script. 

4. 熟悉 Calibre(含TVF及SVRF)或 ICV. 

5. 熟悉 FinFET或 BCD製程為佳。

工作項目： 

1. 開發高效率 NAND flash控制器。 

2. 開發低功耗 NAND flash控制器。 

3. 協助IC設計前後段流程。 

4. 協助IC驗證流程。 

應徵條件： 

1. 學士以上; 電機工程、電信工程、電控工程、電子工程、資訊工程、資訊科學、自動控制、通訊工程相關科系畢業為主。 

2. 具1年以上相關工作經驗，熟悉 NAND flash控制器開發、IC設計/驗證流程者為佳。

工作項目： 

RFC DSP or High speed PHY相關設計。 

應徵條件： 

1. 碩士以上; 電機工程、電信工程、電控工程、電子工程、動力機械、自動控制、通訊工程等相關科系畢業為主。 

2. 無經驗可；具3年以上下列相關經驗之一者尤佳： 

(1) RF相關 calibration(DSP)設計經驗。 

(2) High speed PHY(USB2/3, PCIe, SATA, HDMI)相關設計經驗。 

(3) 熟悉數位 IC設計相關技術及流程者。

工作項目： 

1. 先進製程 IO pad 電路設計, ESD 問題排除. IO pad SI/ PI 分析。 

2. 特殊用途/ 規格 IO 的規格分析，電路設計與開發。 

應徵條件： 

1. 碩士以上；電機電子相關系所畢業，曾修習電子電路設計。 

2. 工作經驗：具備GPIO或DDR IO 電路設計經驗為主, 若有半導體物理, ESD/Latch-up 問題處理經驗尤佳。 

3. 年資不限, 有經驗優先考慮。

工作項目： 

Flash controller電路開發  

應徵條件： 

1. 碩士以上;電機工程、電信工程、資訊工程相關科系畢業為主 

2. 具2年以上數位IC設計相關經驗者為佳 

(MD1880018)

工作項目： 

Digital design verification, including direct test simulation, random test simulation and coverage report. 

應徵條件： 

1. 學士以上; 電機工程、電控工程、電子工程、資訊工程、資訊科學相關科系畢業為主。 

2. 具3年以上數位設計、驗證或 CAD 相關經驗者為佳。

工作項目： 

SoC Physical Design  

應徵條件： 

1. 碩士以上;電機工程、電子工程、資訊工程相關科系畢業為主。 

2. 具0年以上或2至3年相關經驗者為佳。 

(MD1840015)

Key qualifications: 

1. MS degree or above with EE or CS background 

2. Familiar with SystemVerilog and Verilog 

3. Exposure to OVM/UVM/VMM methodology 

4. Exposure to constrained-random based verification environment 

5. Exposure to create coverage model and drive coverage closure in including code/functional coverage. 

6. Be able to develop a test bench from scratch 

7. Hands on working experience on unit/block/full-chip level verification 

8. Good communication skill 

9. Leadership/management experience is a plus. 

Job descriptions: 

1. Plan the verification strategy for SOC projects 

2. Hands-on verification task of some of the units 

3. Work closely with the design teams. 

4. Drive the verification team, problem-solving on day-to-day works 

5. Provide the measurable metrics for project leads and upper management. 

6. Bug/coverage trend identification. Foresee the possible issues and plan for them. 

(MD17C0031)

Key qualifications: 

1. Master degree or above with EE or CS background 

2. Familiar with SystemVerilog and Verilog 

3. Exposure to OVM/UVM/VMM methodology 

4. Exposure to constrained-random based verification environment 

5. Exposure to create coverage model and drive coverage closure in including code/functional coverage. 

6. Be able to develop a test bench from scratch 

Preferred qualifications:  

1. Familiar with PCI/USB/SATA/Serdes 

2. Familiar with Bluetooth 

3. Familiar with SOC bus fabric and AXI/AHB/OCP bus protocols 

4. Familiar DDR2/3/4 

5. Familiar with any type of flash memory 

6. Familiar SVA 

7. Familiar Formal verification methodology 

8. Experience of writing bootloader for ARM/MIPS CPUs 

9. Perl/Python experience 

Job descriptions: 

1. Test plan creation 

2. Develop testbench, test cases, reference model, coverage model and regression suite 

3. Run RTL and gate level simulation, debug failures, manage bug tracking 

4. Drive and achieve coverage closure 

(MD17C0031)

工作項目： 

1. HS design verification. 

2. 開發 USB3.2及 PCIe4.0 

3. DV協助 HS & RFC. 

應徵條件： 

1. 碩士以上; 電機工程、電信工程、電控工程、電子工程、資訊工程、自動控制、通訊工程相關科系畢業為主。 

2. 具 HS/SERDES/DSP相關電路設計經驗者尤佳。 

3. 具 design verification經驗者尤佳。

工作項目： 

IC physical designer (APR)  

應徵條件： 

碩士以上; 電機工程、電子工程、資訊工程相關科系畢業為主