DFT/MBIST engineer for advanced process node & package technology

Responsible for physical design and development activities of MediaTek’s Ghz ARM/Imagination-based graphics processors, AI processors and neural network DS. 

Involve in activities encompass physical design and analysis of complex and timing-critical graphics processor AI processors and neural network DSP. 

Technical disciplines include Physical Implementation (floor-planning, place and route, RC extraction, timing and power optimization) & signoff (DRC, LVS, STA, PI).

1. Architecture design and RTL implementation of Smartphone chipset  

2. Smartphone SoC and mobile computing platform 

design.  

3. System bus and mobile peripheral designs  

4. SoC system performance analysis

1. CPU system design, Power, performance and Area analysis  

2. MCUSYS u-Architecture design  

3. AMBA System bus architecture and integration

1. CPU system design and performance analysis  

2. System bus architecture and integration  

3. IP and system verification

1. SoC Safety Island 的設計、整合與建模 

2. SoC 功能安全的分析、設計、整合與建模 

3. SoC 系統安全與性能分析 

4. 汽車／智慧型手機晶片的架構設計與 RTL 實作

1. 定義供電架構並開發硬體/軟體協同設計技術與策略，以優化系統的電源效能。 

2. 設計微處理器控制器和硬體電路，以及用於智慧型手機與車用產品電源控制相關設計的硬體輔助方案。 

3. 進行耗電與時鐘樹分析，以發掘電源優化的機會。

影像編解碼器硬體架構設計與電路實現

* 根據積體電路設計流程、半導體器件、良率提升等相關知識進行數據分析  

* 建立人工智慧框架與工作流程，以提升數據運營與分析的生產力  

* 與不同的內部及外部團隊溝通協作，提出策略建議

我們正在尋找在半導體設計實現 (semiconductor design enablement) 領域具備深厚背景的專家，主要負責先進製程與封裝 (如 3DIC, CoWoS) 的 PDK 開發及 RC 萃取開發。

1. 應用正規方法在硬體或軟體的驗證上  

2. 正規方法文獻回顧與論文分析以改善目前的使用限制  

3. 規劃安排跨部門的技術教學與討論課程  

4. 相關的文件撰寫與審查修改 

5. 此職缺之薪資起始水準為NT$29500~50000，但仍會視人選之學經歷背景調整核定。

參與先進製程下ASIC及其他產品的開發與導入。  

支援新產品線，如CPO、IVR、cHBM......等技術的設計、驗證與量產導入。  

與跨部門團隊合作，解決產品開發過程中的技術問題，確保專案順利執行。  

持續追蹤先進半導體製程與新穎封裝技術的產業動態，提供技術建議。

我們誠摯招募具高度熱忱且具備一定經驗的製程與元件開發專才，致力於為聯發科技（MediaTek）的內部產品及客製化晶片（ASIC）開發先進製程平台。 在此職務中，您將負責評估最尖端的半導體製程節點（如 2nm、1.4nm、FinFET、GAA/Nanosheet 等），推動設計與技術協同最佳化（DTCO），並確保晶圓代工廠的製程能力與我們的產品藍圖完美契合，以實現最佳的功耗、效能與面積（PPA）表現。  

主要職責：  

1.技術評估、晶圓代工廠合作對接（Foundry Interfacing）以及製程與元件開發。  

2. 元件目標規格設定，以及標準元件庫（Library）／模型（Model）／製程設計套件（PDK）之對齊與驗證。  

3. 製程客製化與Post-silicon tuning，以最大化產品效能。  

4. 推動製程端之設計與技術協同最佳化（Process DTCO）。  

5. 針對良率（Yield）與可靠度（Reliability）開發DFM。  

6. 先進製程技術之先期研究（Process technology pathfinding）。

負責先進製程產品良率改善,應徵者必須有超過3年以上先進製程開發相關經驗.擁有資料中心晶片良率改善或是高速運算中心晶片良率改善經驗優先考慮

1 Develop the Timing/IR signoff criterion for leading process node and 3DIC.  

2 Maintain the Timing/IR signoff criterion ,provide issue solving and consultant for projects on abnormal/unfixable timing/IR violation  

3 Develop new Timing/IR signoff methodology to be applied during chip synthesis/APR/STA/IR .  

4 SPICE correlation for new timing/IR signoff criterion  

5 Regression test for every signoff methodology by STA violation/slack analysis, IR results  

6 Post-silicon data analysis for silicon-proven timing/IR signoff criterion

1. 負責SOC內 bus 數位系統的 SystemC 平台建模與模擬，包括功能建模與性能分析。 

2. 根據系統規格，建立可重複使用且具延展性的 SystemC 模型，支援系統架構規劃與驗證。 

3. 參與 SoC（System-on-Chip）/IP 之行為層及高層次抽象（TLM, Transaction-Level Modeling）模型設計與驗證。 

4. 與硬體、軟體和驗證團隊協同合作，協助流程整合、聯調與問題分析。 

5. 撰寫技術文件與模型說明，支援團隊設計、驗證及客戶應用。

We are looking for talented engineers to join our GPU Architecture team. In this role, you will be at the forefront of defining the next generation of mobile high-performance GPUs. You will be responsible for developing a C++ based model, which serves as the primary tool for architectural exploration, bottleneck analysis, and performance projection before silicon availability. 

Whether you are a fresh graduate with a strong passion for computer architecture or a seasoned veteran in performance modeling, we invite you to help us push the boundaries of graphics rendering and compute efficiency.

Role and Responsibilities 

• Responsible for GPU cluster uArch specification, PPA (power, performance and area) optimization for industry-leading GPU hardware IP 

• Collaborate with Arch/Model/SW team, develop cluster level HW specification that meets feature functionality and PPA metrics 

• Collaborate with Arch/SW/Design team to identify and solve performance bottlenecks, power/area inefficiency issues 

• Guide IP design process all the way from RTL coding, verification to tape out and post-silicon debug 

• Proficiently use AI agent and tools to improve RTL coding, function debug and PPA analysis productivity 

• Execute & deliver to meet milestones/schedules. 

• Analyze and debug code pre-silicon and post-silicon issues. 

• Analyze and influence future GPU architectures. 

• Construct reliable & trustable relationships across teams internally & externally. 

• Delivering best in class GPU IP for mobile, automotive, laptop and ASIC applications

Role and Responsibilities 

• Responsible for GPU cluster uArch specification, PPA (power, performance and area) optimization for industry-leading GPU hardware IP 

• Collaborate with Arch/Model/SW team, develop cluster level HW specification that meets feature functionality and PPA metrics 

• Collaborate with Arch/SW/Design team to identify and solve performance bottlenecks, power/area inefficiency issues 

• Guide IP design process all the way from RTL coding, verification to tape out and post-silicon debug 

• Proficiently use AI agent and tools to improve RTL coding, function debug and PPA analysis productivity 

• Execute & deliver to meet milestones/schedules. 

• Analyze and debug code pre-silicon and post-silicon issues. 

• Analyze and influence future GPU architectures. 

• Construct reliable & trustable relationships across teams internally & externally. 

• Delivering best in class GPU IP for mobile, automotive, laptop and ASIC applications

Role and Responsibilities 

• Responsible for GPU cluster uArch specification, PPA (power, performance and area) optimization for industry-leading GPU hardware IP 

• Collaborate with Arch/Model/SW team, develop cluster level HW specification that meets feature functionality and PPA metrics 

• Collaborate with Arch/SW/Design team to identify and solve performance bottlenecks, power/area inefficiency issues 

• Guide IP design process all the way from RTL coding, verification to tape out and post-silicon debug 

• Proficiently use AI agent and tools to improve RTL coding, function debug and PPA analysis productivity 

• Execute & deliver to meet milestones/schedules. 

• Analyze and debug code pre-silicon and post-silicon issues. 

• Analyze and influence future GPU architectures. 

• Construct reliable & trustable relationships across teams internally & externally. 

• Delivering best in class GPU IP for mobile, automotive, laptop and ASIC applications

Role and Responsibilities 

• Collaborate with architects and design leads to define and document micro architecture of sub-modules of shader subsystem 

• RTL coding and deliver high quality scalable design to meet PPA requirements 

• Collaborate with verification team for feature description, testplan, and coverage closure 

• Assist DV engineers for debugging functional, performance, power test failures 

• Collaborate with synthesis and PD team for timing and area closure 

• Collaborate with power team to identify power saving opportunities and meet power target 

• Assist block team manager in strategy, planning, scope estimation, and progress reporting