DFT/MBIST engineer for advanced process node & package technology

We are looking for a highly experienced PISI Technical Leader to join our team. The ideal candidate will have extensive experience in Power Integrity and Signal Integrity, with a strong background in high-speed IO interface simulations and PDN analysis. As a PISI Technical Leader, you will guide customers through Signal Integrity and Power Integrity signoff, model and optimize system components, and collaborate with various teams to ensure optimal package, PCB, die, interposer, and substrate designs. 

1. Guide customers to complete Signal Integrity and Power Integrity signoff. 

2. Model and optimize vias, connectors, sockets, breakouts, and various system components using commercial tools. 

3. Perform system-level signal integrity simulation in high-speed IOs such as PCIe, SerDes 

4. Architect and simulate power delivery systems, including multiple dies, substrate, interposer, PCBs, and on-die PDN models. 

5. Collaborate with multiple teams, including layout, design, and customers, to optimize package, PCB, die, interposer, and substrate designs.

1. CPU/GPU STA, high-speed & low-voltage timing signoff/ timing closure 方法流程設計  

2. STA 流程開發及應用  

3. high-speed/low-voltage timing signoff criteria開發及應用  

4. 針對project的STA/timing signoff問題進行分析及改善

1. Package design and planning of various product.  

2. Design & layout of BGA substrate.  

3. Co-work with package houses for package design 

4. Development of advanced package technology.  

5. Package design platform development.

1. Perform pre-silicon and post-silicon correlation and modeling related to adaptive voltage scaling and on-die sensor 

2. Develop and improve post-silicon testing methodologies related to adaptive voltage scaling and on-die sensor

1. 數位晶片設計流程與整合 

2. 熟悉低功耗的設計流程(和架構)

1.Smartphone SLT軟體整合(C/Android) 

2.Smartphone SLT量產測試自動化流程改善

• Work with the architecture/micro-architecture/design teams to do white box testing.  

• Create testplans based on the micro-architecture document with the design team. 

• Build, maintain and upgrade testbenches and their components using UVM-based methods. 

• Build custom BFMs for co-sim based module level verification.  

• Add assertions and checkers to facilitate verification.  

• Work with the design team to do module level formal verification. 

• Create controlled random testcases. Pre-debug and provide debug reports. 

• Check functional coverage and code coverage.

• Lead the DV effort of a high-end CPU project. 

• Manage, coach and guide DV engineers. Follow up status and keep up the schedule. 

• Architect and implement top-module testbenches and their components using UVM-based methods.  

• Lead the effort of building in-house BFMs to facilitate co-sim based module level verification.  

• Architect and implement formal verification based module level testbench. 

• Work with the design team to create testplans. Implement checkers/assertions/coverage check points. 

• Work with validation folks to improve design visibility

- RTL/Logic Integration and Verification 

- Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for the blocks and the top level including SOC.  

- Use cdc tool to check RTL/SDC quality 

- Develop Power Intent Specification in UPF for the multi-vdd designs.

• 規劃從silicon bring up到量產全過程的測試程式（包含 CP/FT、系統測試、DVT、HQA、相關性分析及 DPPM 降低）。 

• 開發功能測試/ATPG/MBIST測試碼，涵蓋程式開發、模擬、coverage收集、機台測試程式生成以及在測試機上的驗證。 

• 基於對CPU design的了解以及實驗設計, debug post-silicon DPPM, RMA問題。

負責設計並優化數位相機及影像信號處理領域之IC，與演算法團隊協作，共同開發領先業界的影像處理解決方案，應用於智慧型手機、平板、車用及家庭娛樂等高成長市場。 

工作職責 : 

- 與演算法工程師協作，設計高效能影像信號處理（ISP）/電腦視覺（CV）電路 

- 提供優化硬體方案，達成IC設計「黃金三角」：最小矽面積、極低功耗、最佳影像品質 

- 負責RTL設計、模擬、驗證、邏輯合成與整合流程 

- 參與專案系統架構與技術研討，提出創新設計方案 

- 支援產品跨部門整合及技術溝通

The candidate will conduct functional verification of the RF transceiver circuit design at various stages—from individual circuit blocks to the complete system operation—using behavioral models during the design process.

• New product implementation, especially in Flip Chip related products​ 

• Assembly yield improvement, issue and RMA resolving​ 

• Package technology development and process improvement

1. 使用模擬工具分析汽車SoC的性能、功耗和熱管理指標。 

2. 改進模擬模型，識別並針對SoC最佳化領域。 

3. 實施策略，提升車載SoC的性能和效率。 

4. 自動化評估流程，實現持續的SoC最佳化。 

5. 跟進汽車SoC設計的最新進展，專注於系統層面的改進。

1. 顯示子系統設計(架構, RTL和整合) 

2. 顯示模組IP設計 

3. 顯示界面設計 (如. MIPI-DSI) 

4. 低功耗顯示設計 

5. 顯示系統優化 (PPA, ecosystem SOC/DDIC/LCM) 

6. 顯示技術開發 (手機, 車用, 智能眼鏡等) 

1. Familiar with IC Digital Design, RTL Coding and Integration Flow 

2. Better to have Multimedia or Display Related Experience 

3. Better to have Low Power Design Experience 

4. Better to have Integration Experience 

5. Better to have Display Eco-system Experience

SOC Pre-Silicon 平台技術, 流程方法, 參考設計開發

1. 規劃NPU量產測試程式 

2. 測試及驗證IC功能、性能以及功耗的分析改進 

3. 分析測試資料及測試相關問題，並分析良率問題並改善 

4. AVS low power 的設計

IC設計: 晶片整合 IP開發

Responsible for GPU IC product development, Post-silicon validation, production yield enhancement, and debugging of customer issues. 

負責GPU IC產品開發、IC後段驗證，良率提升，以及客戶問題除錯

1. Familiar with chip digital design flow, including RTL integration, simulation, STA, power analysis 

2. Basic knowledge of analog design 

3. Mixed signal design experience is a plus. 

4. SoC architecture exploration and performance analysis experience is plus. 

5. Post-silicon mass production experience ((Ex: DFT, CP, FT)) is a plus. 

1 . 熟悉數位IC整合流程, 包含RTL, 模擬, 時序分析, 功耗分析, 

2 . 具類比IC設計的基本知識 

3. 混和訊號IC設計經驗是加分項 

4 . 系統架構分析經驗是加分項 

5 . 具IC量產相關經驗(Ex: DFT, CP, FT)是加分項