韌體設計工程師

Responsible for physical design and development activities of MediaTek’s Ghz ARM/Imagination-based graphics processors, AI processors and neural network DS. 

Involve in activities encompass physical design and analysis of complex and timing-critical graphics processor AI processors and neural network DSP. 

Technical disciplines include Physical Implementation (floor-planning, place and route, RC extraction, timing and power optimization) & signoff (DRC, LVS, STA, PI).

1. Architecture design and RTL implementation of Smartphone chipset  

2. Smartphone SoC and mobile computing platform 

design.  

3. System bus and mobile peripheral designs  

4. SoC system performance analysis

1. Bus and Architecture design and RTL implementation of Smartphone chipset 

2. ASIC and Smartphone SoC and mobile computing platform 

design. 

3. System bus and mobile peripheral designs 

4. SoC system performance analysis

1) 負責設計與定義先進4G、5G及6G通訊系統內數據擷取控制系統架構，以作到系統行為分析、系統效能優化，以及問題解決。 

2) 開發、優化並維護數據擷取控制系統的底層驅動程式與軟體控制流程。 

3) 研究並導入以AI為基礎的自動化工具，以強化問題診斷、異常偵測與數據分析能力。

1. 負責多媒體與周邊裝置的軟體及韌體開發（包含框架、驅動程式及功能開發）。 

2. 執行客製化晶片功能驗證。 

3. 進行系統效能優化及問題分析。

1. RTL設計 

2. 數位電路設計  

3. 數位多媒體系統設計  

4. SOC整合  

5. 系統匯流排架構設計

We are looking for a highly skilled DFT CAD and Methodology Expert to develop and deploy advanced test methodologies for next-generation data center and AI ASIC. Enhancing the efficiency and quality of our ASIC development and testing procedures. The successful candidate will work within the CAD team to innovate test solutions for complex 2.5D/3DIC, ensuring high quality and yield for advanced packaging technologies.  

Key Responsibilities 

• Methodology Development: Develop and deploy robust CAD flows for scan insertion, ATPG, pattern simulation, and Memory BIST (MBIST). 

• Tool Automation: Create scripts (Python, TCL, Perl) to enhance and automate DFT flows, accelerating simulation runtimes and improving quality of results (QOR). 

• EDA Tool Integration: Collaborate with EDA vendors to enhance tools for advanced packaging, including test verification and pattern generation. 

• Support & Debug: Support DFT integration teams with CAD flow issues, debug complex issues, and provide technical mentorship. 

• 3DIC/2.5D Expertise: Develop and implement testing strategies for chiplets and TSV-based 3D stacks. 

• Location: Hsinchu, Taipei, Singapore.

We are looking for candidates that can communicate complex engineering subjects effectively to cross functioning technical teams and upper management. Strong DFT and leadership skills will be put to good use. Successful DFT architects interact with many external teams and must confidently represent his/her organization. 

Key Responsibilities 

• Drive DFT Excellence: Define DFT architecture specifications that enhance ATE and production test environments, optimize test costs, and improve quality across future MTK ASIC product portfolios.  

• End-to-End DFT Leadership: Manage comprehensive DFT activities spanning architecture definition, design implementation, verification, and test deployment for new product launches 

• Manufacturing Integration: Serve as a key contributor within MTK’s Global Quality and Operations organization to deliver optimal manufacturing test solutions from early product conception through post-silicon validation 

• Design Collaboration & Quality Assurance: Partner closely with design teams to ensure accurate implementation of DFT structures and compliance with specifications 

• Cross-Functional Team Coordination: Lead internal DFT teams in developing and implementing robust test solutions aligned with architectural requirements 

• Yield Optimization Strategy: Develop comprehensive plans for diagnosability enhancement and systematic yield improvement 

• Location: Hsinchu, Taipei, Singapore, USA

我們正在重新定義晶片設計的未來，不再僅僅是設計電路，而是打造一個能夠「自我演化」的晶片設計大腦。我們正在招募具備 IC 設計與 AI 技術熱忱的工程好手，一起開創 IC 設計新時代！您將與跨領域專家攜手打造 IC Design Autonomous 的未來——運用最先進的 GAI 技術，實現從規格生成、RTL 編碼到自動化 QC 錯誤清除的完整 IC 生命週期自動化，並建立自我進化的生產力循環，讓 AI 真正落地於 IC 設計流程！ 

*任務描述 

- 全流程自動化：設計並實作端到端的自主設計代理人 (Agentic AI) 框架，涵蓋 Spec-to-RTL 與自動化 QC 修復 

- 架構演進：利用 GAI 技術進行 PPA (Power, Performance, Area) 優化，開發具備自我回饋、自我學習能力的設計閉環 

- 技術領導：指導跨團隊協作，將 IC 設計流程中的自動化瓶頸，轉化為 AI 可理解並自主執行的架構 

- 知識體系建構：構建領域專屬的 Knowledge Base 與 Multi-Agent 協作框架 

- 研究創新：研讀最新技術、發表專利論文，將前沿研究轉化為實際應用

* Lead specific architectural domains for SoC architecture design and product technical feasibility studies (e.g., AI, ISP, heterogeneous computing, memory, interconnect, power, safety, vehicle E/E, in-vehicle network). 

* Lead or support automotive SoC architecture, focusing on system performance and power based on product requirements. 

* Lead or support technical feasibility studies of product requirements; collaborate with domain architects and product marketing to develop competitive product design specification. 

* (If manager) Manage the design architecture team, focusing on both technological advancement and talent development.

* Lead specific architectural domains for SoC architecture design and product technical feasibility studies (e.g., AI, ISP, heterogeneous computing, memory, interconnect, power, safety, vehicle E/E, in-vehicle network). 

* Lead or support automotive SoC architecture, focusing on system performance and power based on product requirements. 

* Lead or support technical feasibility studies of product requirements; collaborate with domain architects and product marketing to develop competitive product design specification.

1. 研發 GNSS 基頻訊號處理算法，含 GPS、Galileo、BeiDou、GLONASS、NavIC、QZSS 和 SBAS。 

2. 研發基頻硬體 C-model 和 RTL 設計驗證。 

3. 研發 GNSS HW+SW receiver 於 DSP 嵌入式系統，含 SW 設計、算法實作和系統整合。

1. USB4 Controller Development 

2. Short term =＞ Improve current design quality of USB4 controller 

3. Long term =＞ Next gen USB4 controller architecture define and implementation

We are looking for a highly experienced PISI Technical Leader to join our team. The ideal candidate will have extensive experience in Power Integrity and Signal Integrity, with a strong background in high-speed IO interface simulations and PDN analysis. As a PISI Technical Leader, you will guide customers through Signal Integrity and Power Integrity signoff, model and optimize system components, and collaborate with various teams to ensure optimal package, PCB, die, interposer, and substrate designs. 

1. Guide customers to complete Signal Integrity and Power Integrity signoff. 

2. Model and optimize vias, connectors, sockets, breakouts, and various system components using commercial tools. 

3. Perform system-level signal integrity simulation in high-speed IOs such as PCIe, SerDes 

4. Architect and simulate power delivery systems, including multiple dies, substrate, interposer, PCBs, and on-die PDN models. 

5. Collaborate with multiple teams, including layout, design, and customers, to optimize package, PCB, die, interposer, and substrate designs.

負責開發和維護微控制器單元（MCU）的底層軟體架構與實作， 

此職位需要對 CPU 與低階系統軟體開發有深入了解。 

- 設計、開發和優化 MCU 的軟體，包括初始化程式碼、驅動程式和外設庫。 

- 與硬體工程師合作，確保軟體與 MCU 硬體正確整合。 

- 處理穩定度與能耗相關問題並提供及時解決方案。 

- 與韌體開發人員密切合作，支援在 MCU 平台上的應用程式開發。

1. CPU/GPU STA, high-speed & low-voltage timing signoff/ timing closure 方法流程設計  

2. STA 流程開發及應用  

3. high-speed/low-voltage timing signoff criteria開發及應用  

4. 針對project的STA/timing signoff問題進行分析及改善

1. 針對電視晶片開發影像與視訊處理演算法 

2. 針對電視晶片開發畫質演算法之韌體. 

3. 針對AIPQ, 插幀, 超分, denoise 有經驗 

4. 與硬體設計工程師共同實現演算法於IC. 

5. 與客戶共同開發客製化畫質演算法

1) 訂定通訊系統使用的CPU及系統架構 

2) 開發RTOS、記憶體管理等系統相關服務 

3) 開發CPU及平台模擬器 

4) 分析軟體行為並增進系統效能 

5) 開發CPU及系統相關的驅動及開機流程 

6) 開發自動診斷系統問題的工具

1. Package design and planning of various product.  

2. Design & layout of BGA substrate.  

3. Co-work with package houses for package design 

4. Development of advanced package technology.  

5. Package design platform development.

1. Perform pre-silicon and post-silicon correlation and modeling related to adaptive voltage scaling and on-die sensor 

2. Develop and improve post-silicon testing methodologies related to adaptive voltage scaling and on-die sensor