【2026年暑期實習】類比IC設計

工作項目： 

1. CPU & GPU Backend Implementation (APR) 

2. CPU/GPU Backend Flow Development, Enhancement & Automation 

3. Advanced CPU/GPU Technology Development: High-performance, Low Power, and PPA Optimization 

應徵條件： 

1. 碩士以上；電機、資工、電子相關科系畢業為主。 

2. 熟悉 APR Tools (Innovus、ICC2、Fusion Compiler…)，有Synthesis、STA/IR Analysis、Physical Verification等相關經驗者佳。 

3. 具備程式設計能力，熟悉 TCL/Perl/C++/Python。 

4. 有 High Performance CPU/GPU APR經驗尤佳。 

5. 個性積極負責、勇於迎接新挑戰，對於 High-Performance CPU/GPU Technology 有興趣者。

工作項目： 

1. SSD韌體程式撰寫與設計。 

2. 客製化韌體開發。 

3. 協助檢測 SSD產品、除錯。 

4. 識別問題並提出解決方案。 

應徵條件： 

1. 碩士以上; 電機工程、電信工程、電控工程、電子工程、資訊工程、資訊科學、自動控制相關等科系畢業為主。

工作項目： 

1.PHY (2.5G/10G...) driver developing 

2.SoC/BSP peripheral driver developing 

3.Switch functions developing 

4.Platform and open source developing and maintain, include Linux kernel, lib, open domain utility/software 

應徵條件： 

1.學士以上;電信工程、電控工程、資訊工程、資訊科學、自動控制、通訊工程、以及相關科系畢業為主 

2.具3年以上作經驗 

3.具備： 

1)C programming 

2)Embedded system programming(include linux) 

3)Linux kernel and application programming 

4)TCP/IP stack 

5)Data structure,OS,Algorithm 

6)Unit Test

Key qualifications: 

1. MS degree or above with EE or CS background 

2. Familiar with SystemVerilog and Verilog 

3. Exposure to OVM/UVM/VMM methodology 

4. Exposure to constrained-random based verification environment 

5. Exposure to create coverage model and drive coverage closure in including code/functional coverage. 

6. Be able to develop a test bench from scratch 

7. Hands on working experience on unit/block/full-chip level verification 

8. Good communication skill 

9. Leadership/management experience is a plus. 

Job descriptions: 

1. Plan the verification strategy for SOC projects 

2. Hands-on verification task of some of the units 

3. Work closely with the design teams. 

4. Drive the verification team, problem-solving on day-to-day works 

5. Provide the measurable metrics for project leads and upper management. 

6. Bug/coverage trend identification. Foresee the possible issues and plan for them. 

(MD17C0031)

Key qualifications: 

1. Master degree or above with EE or CS background 

2. Familiar with SystemVerilog and Verilog 

3. Exposure to OVM/UVM/VMM methodology 

4. Exposure to constrained-random based verification environment 

5. Exposure to create coverage model and drive coverage closure in including code/functional coverage. 

6. Be able to develop a test bench from scratch 

Preferred qualifications:  

1. Familiar with PCI/USB/SATA/Serdes 

2. Familiar with Bluetooth 

3. Familiar with SOC bus fabric and AXI/AHB/OCP bus protocols 

4. Familiar DDR2/3/4 

5. Familiar with any type of flash memory 

6. Familiar SVA 

7. Familiar Formal verification methodology 

8. Experience of writing bootloader for ARM/MIPS CPUs 

9. Perl/Python experience 

Job descriptions: 

1. Test plan creation 

2. Develop testbench, test cases, reference model, coverage model and regression suite 

3. Run RTL and gate level simulation, debug failures, manage bug tracking 

4. Drive and achieve coverage closure 

(MD17C0031)

Joining in specification definition, designing verification platform, developing behavioral models, and responsible for system and functional verification

工作項目： 

SSD專案 Leader，帶領團隊開發 SSD產品。 

應徵條件： 

1. 碩士以上; 電機工程、電信工程、電控工程、電子工程相關科系畢業為主。 

2. 具5年以上相關工作經驗： 

(1) 精通 SATA interface protocol. 

(2) 精通 PCIe interface protocol. 

(3) 精通 NAND flash protocol. 

(4) 精通 LDPC演算法。 

(5) 精通 Digital design流程或具其他相關經驗者為佳。