運算系統架構工程師 (Benchmark 最佳化)

加入 MediaTek「先進製程平台 DFT」團隊，你的工作直接影響 N4/N3/N2 及更先進世代 Cloud ASIC 的可靠度與良率。  

- DFT 架構與插入：針對先進節點 SoC 及 chiplet/3D-IC 設計，定義並實作 Scan（full-scan、compressor）、MBIST、BSD/JTAG 架構；使用 Synopsys / Siemens (Tessent) EDA 工具執行端到端插入流程。  

- ATPG 與 Advanced Fault Model：開發並優化 stuck-at、transition delay、cell-aware、path-delay 等 fault model 的 ATPG pattern；驅動 fault coverage closure 並交付 DRC-clean pattern。  

- 模擬與驗證：透過 gate-level simulation（VCS/Xcelium）驗證 DFT 邏輯正確性；解決 DFT rule violation 與 coverage gap，確保 tapeout 品質。  

- 後矽驗證與測試：主導 CP / FT / HTOL / HVS 各階段 DFT 工作，包含 test mode 驗證、scan chain 連通性測試、MBIST 執行與 repair 確認。 - Volume Diagnosis 與 Yield Ramp：運用 scan/MBIST diagnosis 資料分離系統性缺陷，與製程及 FA 團隊協作加速 yield learning 與技術成熟。  

- RMA / DPPM 除錯：利用 DFT diagnosis 流程調查 field return，協助降低 DPPM 並防止 escape。  

- 產業前沿：持續追蹤 Cloud ASIC chiplet 測試趨勢、ATE 技術進展與 EDA 新功能，主動將新觀念帶入團隊。 

職務要求

Responsible for GPU HW development environment tool/flow maintenance and database (perforce) management. Effectively support DE/DV smooth development.

1. Work on AI development for design flow  

2. Perform floorplan, clock planning, place and route, timing closure, ECO, IR signoff flow automation

1. 5G/6G通訊IP開發. 

2. 多模(5G/6G)解調架構開發以及RTL coding/verification/integration.

1. Familiar with DFT plan, methodology, implementation 

2. Familiar with new DFT flow such as SSN, HSIO 

3. Familar with STA, timing analysis

1. SoC low power design, integration, and modeling 

2. SoC adaptive voltage scaling development

We are looking for a DFT Engineer to define and implement DFT architectures for data center ASIC products. The role involves developing test strategies, integrating DFT features, and improving test coverage for mass production. You will work closely with design teams to ensure robust DFT solutions, yield improvement, and quality.  

Key Responsibilities 

• Develop and optimize test strategies to achieve coverage and manufacturing goals; analyze and improve test coverage. 

• Integrate DFT features at RTL and gate-level, supporting both top and block-level DFT planning and implementation. 

• Perform ATPG, fault simulation, and coverage analysis. 

• Collaborate with BE and PD teams to ensure DFT-friendly timing and support IR convergence in test mode. 

• Lead silicon bring-up and debug of test features; conduct failure and yield analysis. 

• Work with product teams to facilitate pattern generation, validation, and DPPM improvement.

We are looking for candidates that can communicate complex engineering subjects effectively to cross functioning technical teams and upper management. Strong DFT and testing skills will be put to good use. Successful handling with many external teams from pre-silicon phase cross to post-silicon on advance silicon and assembly process. Key Responsibilities  

• Drive DFT Excellence: Define DFT architecture specifications that enhance ATE and production test environments, optimize test costs, and improve quality across future MTK ASIC product portfolios.  

• Product test planning capability: Manage comprehensive post-silicon flow optimization, and test deployment for new product launches  

• Manufacturing Integration: Serve as a key contributor within MTK’s Global Quality and Operations organization to deliver optimal manufacturing test solutions from early product conception through post-silicon validation  

• Design Collaboration & Quality Assurance: Partner closely with design teams to ensure accurate implementation of DFT structures and compliance with specifications.

1. Bus and Architecture design and RTL implementation of Smartphone chipset 

2. ASIC and Smartphone SoC and mobile computing platform 

design. 

3. System bus and mobile peripheral designs 

4. SoC system performance analysis

1. RTL設計 

2. 數位電路設計  

3. 數位多媒體系統設計  

4. SOC整合  

5. 系統匯流排架構設計

We are looking for a highly skilled DFT CAD and Methodology Expert to develop and deploy advanced test methodologies for next-generation data center and AI ASIC. Enhancing the efficiency and quality of our ASIC development and testing procedures. The successful candidate will work within the CAD team to innovate test solutions for complex 2.5D/3DIC, ensuring high quality and yield for advanced packaging technologies.  

Key Responsibilities 

• Methodology Development: Develop and deploy robust CAD flows for scan insertion, ATPG, pattern simulation, and Memory BIST (MBIST). 

• Tool Automation: Create scripts (Python, TCL, Perl) to enhance and automate DFT flows, accelerating simulation runtimes and improving quality of results (QOR). 

• EDA Tool Integration: Collaborate with EDA vendors to enhance tools for advanced packaging, including test verification and pattern generation. 

• Support & Debug: Support DFT integration teams with CAD flow issues, debug complex issues, and provide technical mentorship. 

• 3DIC/2.5D Expertise: Develop and implement testing strategies for chiplets and TSV-based 3D stacks. 

• Location: Hsinchu, Taipei, Singapore.

We are looking for candidates that can communicate complex engineering subjects effectively to cross functioning technical teams and upper management. Strong DFT and leadership skills will be put to good use. Successful DFT architects interact with many external teams and must confidently represent his/her organization. 

Key Responsibilities 

• Drive DFT Excellence: Define DFT architecture specifications that enhance ATE and production test environments, optimize test costs, and improve quality across future MTK ASIC product portfolios.  

• End-to-End DFT Leadership: Manage comprehensive DFT activities spanning architecture definition, design implementation, verification, and test deployment for new product launches 

• Manufacturing Integration: Serve as a key contributor within MTK’s Global Quality and Operations organization to deliver optimal manufacturing test solutions from early product conception through post-silicon validation 

• Design Collaboration & Quality Assurance: Partner closely with design teams to ensure accurate implementation of DFT structures and compliance with specifications 

• Cross-Functional Team Coordination: Lead internal DFT teams in developing and implementing robust test solutions aligned with architectural requirements 

• Yield Optimization Strategy: Develop comprehensive plans for diagnosability enhancement and systematic yield improvement 

• Location: Hsinchu, Taipei, Singapore, USA

我們正在重新定義晶片設計的未來，不再僅僅是設計電路，而是打造一個能夠「自我演化」的晶片設計大腦。我們正在招募具備 IC 設計與 AI 技術熱忱的工程好手，一起開創 IC 設計新時代！您將與跨領域專家攜手打造 IC Design Autonomous 的未來——運用最先進的 GAI 技術，實現從規格生成、RTL 編碼到自動化 QC 錯誤清除的完整 IC 生命週期自動化，並建立自我進化的生產力循環，讓 AI 真正落地於 IC 設計流程！ 

*任務描述 

- 全流程自動化：設計並實作端到端的自主設計代理人 (Agentic AI) 框架，涵蓋 Spec-to-RTL 與自動化 QC 修復 

- 架構演進：利用 GAI 技術進行 PPA (Power, Performance, Area) 優化，開發具備自我回饋、自我學習能力的設計閉環 

- 技術領導：指導跨團隊協作，將 IC 設計流程中的自動化瓶頸，轉化為 AI 可理解並自主執行的架構 

- 知識體系建構：構建領域專屬的 Knowledge Base 與 Multi-Agent 協作框架 

- 研究創新：研讀最新技術、發表專利論文，將前沿研究轉化為實際應用

* Lead specific architectural domains for SoC architecture design and product technical feasibility studies (e.g., AI, ISP, heterogeneous computing, memory, interconnect, power, safety, vehicle E/E, in-vehicle network). 

* Lead or support automotive SoC architecture, focusing on system performance and power based on product requirements. 

* Lead or support technical feasibility studies of product requirements; collaborate with domain architects and product marketing to develop competitive product design specification. 

* (If manager) Manage the design architecture team, focusing on both technological advancement and talent development.

* Lead specific architectural domains for SoC architecture design and product technical feasibility studies (e.g., AI, ISP, heterogeneous computing, memory, interconnect, power, safety, vehicle E/E, in-vehicle network). 

* Lead or support automotive SoC architecture, focusing on system performance and power based on product requirements. 

* Lead or support technical feasibility studies of product requirements; collaborate with domain architects and product marketing to develop competitive product design specification.

1. USB4 Controller Development 

2. Short term =＞ Improve current design quality of USB4 controller 

3. Long term =＞ Next gen USB4 controller architecture define and implementation

We are looking for a highly experienced PISI Technical Leader to join our team. The ideal candidate will have extensive experience in Power Integrity and Signal Integrity, with a strong background in high-speed IO interface simulations and PDN analysis. As a PISI Technical Leader, you will guide customers through Signal Integrity and Power Integrity signoff, model and optimize system components, and collaborate with various teams to ensure optimal package, PCB, die, interposer, and substrate designs. 

1. Guide customers to complete Signal Integrity and Power Integrity signoff. 

2. Model and optimize vias, connectors, sockets, breakouts, and various system components using commercial tools. 

3. Perform system-level signal integrity simulation in high-speed IOs such as PCIe, SerDes 

4. Architect and simulate power delivery systems, including multiple dies, substrate, interposer, PCBs, and on-die PDN models. 

5. Collaborate with multiple teams, including layout, design, and customers, to optimize package, PCB, die, interposer, and substrate designs.

1. CPU/GPU STA, high-speed & low-voltage timing signoff/ timing closure 方法流程設計  

2. STA 流程開發及應用  

3. high-speed/low-voltage timing signoff criteria開發及應用  

4. 針對project的STA/timing signoff問題進行分析及改善

1. Package design and planning of various product.  

2. Design & layout of BGA substrate.  

3. Co-work with package houses for package design 

4. Development of advanced package technology.  

5. Package design platform development.

1. Perform pre-silicon and post-silicon correlation and modeling related to adaptive voltage scaling and on-die sensor 

2. Develop and improve post-silicon testing methodologies related to adaptive voltage scaling and on-die sensor