韌體設計工程師

1. 數位設計GAI IDE平台架構需求分析、設計與整合。 

2. 數位設計GAI應用開發與測試。 

3. 數位設計GAI prompt engineering/RGA/AI-agent框架開發與測試。

28nm及以下先進製程(含FinFET) IO電路和ESD防護設計, 工作內容包含  

(1) GPIO電路設計(包含ESD/LU防護) 

(2) 特殊應用IO (SD3.0/SIM card/eMMC等)電路設計(包含ESD/L防護)  

(3) 高速IO和特殊應用IO在事業部專案上展開和執行 

- Advance node (28nm and beyond, including FetFET) IO circuitry and ESD protection design covering fields for  

(a) General purpose IO circuit design (with ESD/LU protection)  

(b) Specialty IO (SD3.0/SIM card/eMMC etc.) circuit design (with ESD/LU protection)  

(c) Project related implementation for high speed/specialty IO Interface - High speed IO, specialty IO circuit design, ESD protection circuit design and simulation.  

Work with project leader, layout, packaging and system engineers to meet design and system specifications.  

Work with IO library modeling, characterization teams closely for IP release.

AI Model development, system level modeling and HW/SW system level bottleneck analysis

1. CPU功耗分析 (設計 vs. 量測), 確保CPU功耗體質  

2. CPU最大電流分析 (設計 vs. 量測), 驗證過電流保護機制確保系統穩定性  

3. PMIC+PDN+CPU 功耗效率優化 

1. CPU power pre-silicon vs. post-silicon correlation. Ensure CPU power quality  

2. CPU max. current pre-silicon vs. post-silicon correlation. Validate max. current protection technique for system stability  

3. PMIC+PDN+CPU power efficient optimization

CPU Physical design, - floorplanning, - timing closure - Physical verficiation - DFT

1. 開發emulation/prototyping 相關的技術及使用流程 

2. 建立CPU/GPU emulation/prototyping 驗證平台 

3. 協助project team導入emulation/prototyping 技術 

4. emulation/prototyping 使用及工具問題的支持 

5. 管理 emulator 及prototyping 硬體與使用分配

SoC Power/IR/PI 專家，可以處理與 IR 相關的主題和問題，例如專案執行過程中 IR drop 發生原因、熱點解決以及改進 IR 分析和預防流程。 同時具備SoC，封裝，及系統版電源分析知識

無線通訊設計驗證 

包含 Test plan 規劃, Bench, VIP 建立, test case 撰寫, 完成coverage等相關驗証工作

1. AI ISP 硬體架構設計 

2. 系統power 與 bandwidth 設計 

3. 相機規格制訂 

4. ISP 硬體系統規格驗證規劃 

5. 車用安全規劃

1.Propose design verification plan and do the execution based on IP and system HW architecture/application 

2.Develop design verification environment 

3.Develop required verification methodology and adopt into project

聯發科技以先進多媒體技術聞名，數位視訊解碼更為多媒體技術中之重要一環，如果您對Multi-format Video decoder架構設計 / RTL implementation / 整合驗證有興趣，聯發科技誠摯邀請您，與全球最頂尖的菁英一同合作，彼此激盪最新的創意與解法，共同挑戰每一個不可能。

1. 規劃量產測試以及量產functin pattern porting 

2. 測試以及驗證IC功能，性能，以及功耗等等相關測試 

3. 分析測試資料以及釐清相關測試的問題，並分析良率問題以及良率改善建議 

4. AVS low power的設計

1. Develop systematic algorithms to alleviate design challenges, including implementation, process what-if assessment, system performance evaluation, in advanced nodes or package 

2. Closely work with foundry and EDA vendors to define innovative HPC, Chiplet design methodologies 

3. Explore new EDA features and define improvement direction from MTK product requirements

1. 新產品開發討論 

2. 電源管理IC及電源管理單元晶片整合 

3. 與設計/生產/品保/軟體部門溝通協調 

4. 晶片開發滿足智慧手機, IOT, 車用, 以及ASIC的需求

1. 電源管理晶片架構與系統設計(手機/車用) 

2. 低功耗設計技術開發 

3. 混合訊號數位 IP 設計: voltage regulator, ADC, system clocking and start-up, TOP infra/bus, peripheral designs 

4. 電源管理晶片整合: front-end and back-end integration

1. 平台電源管理系統架構設計與規格定義, 包含功耗/溫度/性能等系統分析. 

2. 系統應用詳細電源需求與控制架構之分析與優化 

3. 電源管理芯片規格制定與新技術之開發.

1. DFT architecture exploration & evaluation for next-gen process node & package technology of MediaTek: 

* Scan chain insertion & ATPG pattern generation 

* Pattern validation through simulation & silicon analysis(pass/fail, shmoo, fail log, etc.) 

* Diagnosis to help manufacture process improvement 

2. Co-work with SoC architect, RTL designer, physical design engineer, and package engineer to define best architecture for 3D-IC: 

* PPA(Performance/Power/Area) impact analysis & mitigation via DFT innovation 

* Develop & integrate DFT-related RTL design modules to test chip

Work in Analog/Mixed-Signal Modeling and Verification Methodology Development group to establish, streamline and enhance new and existing AMS Behavioral Modeling related development method, coding and validation process and integration flows, and work hands-on with AMS IP Teams for AMS Behavioral Modeling flow and process experiments, demonstrations, adaptions, and deployment. The candidate will work with AMS IP teams including digital design, analog design, analog behavioral modeling and design verification members, apply and advance existing and evolving AMS Behavioral Modeling methodologies and processes, and contribute to establish and maintain Modeling Platform to ensure High Quality and High Efficiency of Pre-Si AMS Modeling, Validation and Verification delivery towards high quality silicon products. 

• Work in methodology development group to establish, streamline and enhance new and existing AMS Behavioral Modeling related development method, coding and validation process and integration flows. 

• Work with teams to enable deployment of new AMS Behavioral Modeling flow and processes through experiments, demonstrations, adaptions (for real projects in specified areas such as RF, etc) and integration.  

• Document on new flows and processes for AMS Behavioral Modeling. 

• Apply wide range of AMS Behavioral Modeling skills to help and support AMS IP or Chip Teams to establish or enhance new or existing Modeling capabilities, including but not limited to Model Development, Model Validation to ensure Consistency of Behavior with Original Circuit, Integration of Models into various Verification Environment, fixing Modeling issues found in simulation, etc.  

• Contribute to continuous improving on AMS Behavioral Modeling process for better quality and efficiency through methodology and process improvements.  

• Communicate and collaborate with global architecture, design, verification teams to address new needs or requirement on AMS Behavioral Modeling. 

Job Locations: 

• Taiwan:Hsinchu/Taipei 

• India: Bangalore 

• Singapore 

• USA:Santa Clara, CA/San Diego, CA

Work in Analog/Mixed-Signal Design Verification Methodology Development group to establish, streamline and enhance new and existing AMS DV related development method, coding process and integration flows, and work hands-on with AMS IP Teams for AMS DV flow and process experiments, demonstrations, adaptions, and deployment. The candidate will work with digital design, analog design, analog behavioral modeling and design verification teams, apply and advance existing and evolving Digital and AMS Verification methodologies and processes, and contribute to establish and maintain Verification Platform to ensure High Quality and High Efficiency of Pre-Si Verification Delivery towards high quality silicon products.  

• Work in methodology development team to establish, streamline and enhance new and existing AMS DV related development method, coding process and integration flows. 

• Work with teams to enable deployment of new flow and processes through experiments, demonstrations, adaptions (for real projects in specified areas such as SERDES, etc) and integration.  

• Document on new flows and processes for AMS DV. 

• Apply wide range of Digital and/or AMS DV skills to help and support AMS IP or Chip DV Teams to establish or enhance new or existing DV capabilities, including but not limited to developing scalable and portable Test bench, test cases, drivers, checkers, assertions and reference models, and running RTL and Gate Level simulations and reaching all coverage closures.  

• Contribute to continuous improving on AMS DV process for better quality and efficiency through methodology and process improvements.  

• Communicate and collaborate with global architecture, design, verification, and post-Silicon testing teams to address new needs or requirement on DV Support. 

Job Locations: 

• Taiwan:Hsinchu/Taipei 

• India: Bangalore 

• Singapore 

• USA:Santa Clara, CA/San Diego, CA

1. Work on 3~7nm design implementation, methodology, and sign-off 

2. Perform synthesis, DFT, floorplan, clock planning, place and route, timing closure, ECO, IR signoff, and physical verification 

3. Manage schedule, resolve design and flow issues, drive methodologies and execution