韌體設計工程師

1. Develop scalable platform clocking architecture for automotive SoC 

2. Enhance SoC clock architecture and technology development to address the automotive SoC requirements 

3. Drive clock architecture and designs to optimize power, performance, and implementation, including physical design and timing closure

We are seeking skilled engineers for designing high-performance Virtualization and Interconnect Architecture and developing RTL for both Automotive and High-Performance Computing. 

Roles: 

1. Develop, assess, and refine RTL to achieve performance, power, area, and timing goals. 

2. Develop micro-architecture by exploring early high-level macro architectures, researching micro-architecture, and defining detailed specifications. 

3. Coordinate co-design efforts between architecture, software, and hardware teams to achieve functional realization. 

4. Develop and implement interconnect methodologies, such as simulation, emulation, implementation, and efficiency improvement.

1. Define power states and management hardware architecture for optimal power performance. 

2. Design microprocessor-based power management controller and HW assistance designs. 

3. Define power architecture by performing power rail tradeoff analysis with adaptive voltage scaling consideration

1.從系統應用功秏分析, 與 IP, SoC 與軟體團隊合作, 推進 SoC low power 軟硬體架構的演進. 

2.產品規格定義時, 分析不同架構與 IP 選項, 在系統應用功秏體驗的差異, 產出產品應用 power dash board, 提供產品規格決策的依據. 

3.執行或協助功秏量測, 與power model預估的功秏做校正 

4.分析PMIC/Power rail 設計, SoC power state 與 data-path power等, 並且提出SOC 設計優化方案 

5.提出系統優化的方向, 達到最佳的產品電池使用續航時間與使用體驗

- Logic/Physical Synthesis by using advanced optimization techniques(below N7) and generate optimized Gate Level Netlist for Timing, Area, Power. 

- Debug the timing/area/congestion issues and work with RTL & Physical designers to resolve them. 

- Run Formal Verification checks between RTL and Gate level netlist and debug the aborts, inconclusive and Logic Equivalency failures. 

- DFT insertion, ATPG and gate-level simulation 

- Developing Automation scripts and Methodology for all FE-tools including (Lint, CDC, RDC, Synthesis, STA, Power). 

- Interact with Physical Design Engineers and provide them with timing/congestion feedback.

1. 開發, 優化與維護 4G/5G Modem 自動化整合測試平台, CI Flow 等. 

2. 開發, 優化與維護 4G/5G Modem Simulator  

3. 開發, 優化與維護 4G/5G Modem 研發流程與驗證平台的 Tool Chain

協助電源管理晶片規格製定, 新 IP 開發規劃及產品驗證協助類比晶片IP開發, 驗證.

1. Work on 7nm~3nm design implementation, methodology, and sign-off 

2. Perform synthesis, DFT, floorplan, clock planning, place and route, timing closure, ECO, IR signoff, and physical verification 

3. Manage schedule, resolve design and flow issues, drive methodologies and execution

開發手機/平板SoC模擬及分析平台， 

從系統效能，功率消耗，溫度控制...等多重面向分析產品競爭力， 

進而從系統角度優化硬體架構及軟體控制策略。

* Define and optimize SOC hardware architecture and associated software flows in aspects of system performance/power/area to improve MediaTek‘s product competitiveness. 

* Develop simulation and analysis platforms for performance/power/area analysis. 

* Work Loction : HsinChu, Taipei

1. Work on 7nm~3nm design implementation, methodology, and sign-off 

2. Perform synthesis, DFT, floorplan, clock planning, place and route, timing closure, ECO, IR signoff, and physical verification 

3. Manage schedule, resolve design and flow issues, drive methodologies and execution