SOC System Architect

1. Develop 3.5D methodology from RTL to GDS and Package 

2. Coordinate Thermal and PI/SI team to deal with high power design 

3. Execute the project at different phases

1. 整合IR 資訊和內部團隊合作解決 IR 問題 

2. 產生並分析 power 資訊 

3. 和客戶溝通 IR 相關的 methodology 並開發流程解決問題

1. 數位晶片設計流程與整合  

2. 熟悉低功耗的設計流程(和架構)

1. Develop and implement DRAM controller/PHY solutions for data-center applications. Validate functionality, improve design to optimize performance, power, latency and efficiency. 

2. Memory controller/PHY Integration: Design and integration memory system.

We are looking for a Senior DFT Engineer to define and implement DFT architectures for data center ASIC products. The role involves developing test strategies, integrating DFT features, and improving test coverage for mass production. You will work closely with design teams to ensure robust DFT solutions, yield improvement, and quality.  

Key Responsibilities 

• Develop and optimize test strategies to achieve coverage and manufacturing goals; analyze and improve test coverage. 

• Integrate DFT features at RTL and gate-level, supporting both top and block-level DFT planning and implementation. 

• Perform ATPG, fault simulation, and coverage analysis. 

• Collaborate with BE and PD teams to ensure DFT-friendly timing and support IR convergence in test mode. 

• Lead silicon bring-up and debug of test features; conduct failure and yield analysis. 

• Work with product teams to facilitate pattern generation, validation, and DPPM improvement.

1. 旗艦智慧型手機晶片整合  

2. 車用系統晶片整合  

3. Clock架構  

4. Timing收斂與分析  

5. DFT/Test mode整合驗證

1. Architecture design and RTL implementation of Automotive/Smartphone chipset 

2. SoC system power and performance analysis 

3. SoC system bus and memory subsystem design, integration, and modeling 

4. SoC low power design, integration, and modeling 

5. SoC functional safety analysis, design, integration, and modeling 

6. SoC cyber security analysis, design, integration, and modeling

車用相關 IC 設計流程專家。 具備車用SoC/ASIC RTL2GDS 實做經驗和問題解決能力。 同時具備車用IC設計流程中 Safety mechanism 的專業知識。

1. Architecture design and RTL implementation for Smartphone and automotive chip 

2. Smartphone SoC and mobile computing platform design.  

3. System bus and high speed interface designs

We are seeking a highly skilled DFT/DFM Engineer to join our automotive ADAS SoC chip design team.  

The successful candidate will be responsible for DFT and DFM methodologies, design, and implementation for our advanced automotive system-on-chip (SoC) designs.  

The candidate will also collaborate with the design and layout teams to integrate DFT/DFM requirements. 

• SoC testing architecture design  

• Support project NPI(new product introduction) to MP(mass production) (test program development, coverage enhancement, yield improvement, cost reduction) 

• Cowork w/ IP, test engineer, process team, board design to fulfill CP/FT/SLT test requirement.

1. Smartphone (Low Power Architect) and Automotive (Power control) 

2. Not a management position 

3. Short term:digital IP design/integration of power control IPs with zero bugs  

Long term:define power control arch for smartphone or automotive products 

develop new tech for power control

1. Develop and implement tailored DRAM controller/PHY solutions for automotive applications. Validate functionality, improve design revisions and meet performance targets as well as system requirements. 

2. Perform rigorous design testing and debugging in automotive environments. Troubleshoot and propose solutions for any issues occurring in post-silicon validation. 

3. System Level Cache Design & Implementation: Design and implement system level cache strategies to optimize performance and efficiency across our product range. 

4. System-Level Understanding: Exhibit a system-level understanding of performance trade-offs, system architecture, memory subsystems, and various memory technologies (DDR3, DDR4, DDR5, LPDDR3, LPDDR4, LPDDR5 etc.). 

5 . Ensure that all designs comply with automotive industry standards and regulations, such as ISO 26262 and Automotive SPICE.

1. Develop high speed interface subsystem architecture and integrate PCIe, MIPI, or DisplayPort subsystem. 

2. Develop security and FuSa function on PCIe, MIPI, or DisplayPor degital circuit.

解讀客戶的網絡安全需求 

從網絡安全需求中推導出功能和安全概念 

制定和審查安全系統架構 

與 IP 團隊和客戶溝通和協調安全設計 

執行系統安全分析（例如：TARA）

1. Interpret customers’ functional safety requirements 

2. Derive functional and technical safety concepts from functional safety requirements 

3. Develop and review the safety IP design 

4. Communicate and coordinate safety designs with IP teams 

5. Perform system safety analysis (ex: FMEDA)

1. Interpret customers’ functional safety requirements into SoC requirements 

2. Define the SoC level architectures to meet functional safety requirements 

3. Communicate and coordinate safety designs with cross-function IP teams 

4. Perform system safety analysis (ex: FMEDA)

1.數位電路設計  

2.多媒體架構與電路設計  

3.多媒體系統整合 

1.Digital IC Design 

2.Multimedia Architecture and Design 

3.Multimedia System Integration

Wi-Fi架構和數位電路設計 

整個晶片的時鐘、測試和重置規劃 

低功耗數位設計 

從RTL到閘級的SoC晶片整合，包括時序收斂和可測試性 

設計方法和整合流程改進

1. Processor core, cache and peripheral verification 

2. Verification flow and methodology 

3. Advanced tool and verification technology survey

1. Serdes/High speed interface related PHYD IP architecture planning. 

2. Serdes/High speed interface related PHYD IP RTL coding.  

3. Serdes/High speed interface related PHYD IP front-end and back-end integration.  

4. Co-work with MAC design team and DV team for IP verification.  

5. Co-work with Analog design team for PHY co-simulation.