電源管理IC應用工程師

Responsible for physical design and development activities of MediaTek’s Ghz ARM/Imagination-based graphics processors, AI processors and neural network DS. 

Involve in activities encompass physical design and analysis of complex and timing-critical graphics processor AI processors and neural network DSP. 

Technical disciplines include Physical Implementation (floor-planning, place and route, RC extraction, timing and power optimization) & signoff (DRC, LVS, STA, PI).

1. Architecture design and RTL implementation of Smartphone chipset  

2. Smartphone SoC and mobile computing platform 

design.  

3. System bus and mobile peripheral designs  

4. SoC system performance analysis

1. CPU system design, Power, performance and Area analysis  

2. MCUSYS u-Architecture design  

3. AMBA System bus architecture and integration

1. CPU system design and performance analysis  

2. System bus architecture and integration  

3. IP and system verification

1. SoC Safety Island 的設計、整合與建模 

2. SoC 功能安全的分析、設計、整合與建模 

3. SoC 系統安全與性能分析 

4. 汽車／智慧型手機晶片的架構設計與 RTL 實作

1. 定義供電架構並開發硬體/軟體協同設計技術與策略，以優化系統的電源效能。 

2. 設計微處理器控制器和硬體電路，以及用於智慧型手機與車用產品電源控制相關設計的硬體輔助方案。 

3. 進行耗電與時鐘樹分析，以發掘電源優化的機會。

影像編解碼器硬體架構設計與電路實現

我們正在尋找在半導體設計實現 (semiconductor design enablement) 領域具備深厚背景的專家，主要負責先進製程與封裝 (如 3DIC, CoWoS) 的 PDK 開發及 RC 萃取開發。

1. 應用正規方法在硬體或軟體的驗證上  

2. 正規方法文獻回顧與論文分析以改善目前的使用限制  

3. 規劃安排跨部門的技術教學與討論課程  

4. 相關的文件撰寫與審查修改 

5. 此職缺之薪資起始水準為NT$29500~50000，但仍會視人選之學經歷背景調整核定。

1. 負責SOC內 bus 數位系統的 SystemC 平台建模與模擬，包括功能建模與性能分析。 

2. 根據系統規格，建立可重複使用且具延展性的 SystemC 模型，支援系統架構規劃與驗證。 

3. 參與 SoC（System-on-Chip）/IP 之行為層及高層次抽象（TLM, Transaction-Level Modeling）模型設計與驗證。 

4. 與硬體、軟體和驗證團隊協同合作，協助流程整合、聯調與問題分析。 

5. 撰寫技術文件與模型說明，支援團隊設計、驗證及客戶應用。

We are looking for talented engineers to join our GPU Architecture team. In this role, you will be at the forefront of defining the next generation of mobile high-performance GPUs. You will be responsible for developing a C++ based model, which serves as the primary tool for architectural exploration, bottleneck analysis, and performance projection before silicon availability. 

Whether you are a fresh graduate with a strong passion for computer architecture or a seasoned veteran in performance modeling, we invite you to help us push the boundaries of graphics rendering and compute efficiency.

Role and Responsibilities 

• Responsible for GPU cluster uArch specification, PPA (power, performance and area) optimization for industry-leading GPU hardware IP 

• Collaborate with Arch/Model/SW team, develop cluster level HW specification that meets feature functionality and PPA metrics 

• Collaborate with Arch/SW/Design team to identify and solve performance bottlenecks, power/area inefficiency issues 

• Guide IP design process all the way from RTL coding, verification to tape out and post-silicon debug 

• Proficiently use AI agent and tools to improve RTL coding, function debug and PPA analysis productivity 

• Execute & deliver to meet milestones/schedules. 

• Analyze and debug code pre-silicon and post-silicon issues. 

• Analyze and influence future GPU architectures. 

• Construct reliable & trustable relationships across teams internally & externally. 

• Delivering best in class GPU IP for mobile, automotive, laptop and ASIC applications

Role and Responsibilities 

• Responsible for GPU cluster uArch specification, PPA (power, performance and area) optimization for industry-leading GPU hardware IP 

• Collaborate with Arch/Model/SW team, develop cluster level HW specification that meets feature functionality and PPA metrics 

• Collaborate with Arch/SW/Design team to identify and solve performance bottlenecks, power/area inefficiency issues 

• Guide IP design process all the way from RTL coding, verification to tape out and post-silicon debug 

• Proficiently use AI agent and tools to improve RTL coding, function debug and PPA analysis productivity 

• Execute & deliver to meet milestones/schedules. 

• Analyze and debug code pre-silicon and post-silicon issues. 

• Analyze and influence future GPU architectures. 

• Construct reliable & trustable relationships across teams internally & externally. 

• Delivering best in class GPU IP for mobile, automotive, laptop and ASIC applications

Role and Responsibilities 

• Responsible for GPU cluster uArch specification, PPA (power, performance and area) optimization for industry-leading GPU hardware IP 

• Collaborate with Arch/Model/SW team, develop cluster level HW specification that meets feature functionality and PPA metrics 

• Collaborate with Arch/SW/Design team to identify and solve performance bottlenecks, power/area inefficiency issues 

• Guide IP design process all the way from RTL coding, verification to tape out and post-silicon debug 

• Proficiently use AI agent and tools to improve RTL coding, function debug and PPA analysis productivity 

• Execute & deliver to meet milestones/schedules. 

• Analyze and debug code pre-silicon and post-silicon issues. 

• Analyze and influence future GPU architectures. 

• Construct reliable & trustable relationships across teams internally & externally. 

• Delivering best in class GPU IP for mobile, automotive, laptop and ASIC applications

Role and Responsibilities 

• Collaborate with architects and design leads to define and document micro architecture of sub-modules of shader subsystem 

• RTL coding and deliver high quality scalable design to meet PPA requirements 

• Collaborate with verification team for feature description, testplan, and coverage closure 

• Assist DV engineers for debugging functional, performance, power test failures 

• Collaborate with synthesis and PD team for timing and area closure 

• Collaborate with power team to identify power saving opportunities and meet power target 

• Assist block team manager in strategy, planning, scope estimation, and progress reporting

- Collaborate with architects and cross-functional teams to understand GPU specs and define verification strategies. 

- Develop SystemVerilog/UVM test frameworks and co-simulation environments; verify GPU logic at unit, subsystem, and top levels. 

- Create and execute verification test plans, focusing on functional coverage. 

- Generate random and directed test sequences; maintain testbench, scoreboard, BFMs, and regression. 

- Perform RTL and coverage analysis; optimize test scenarios and address bug escapes. 

- Support performance verification, emulation, data collection, debugging, and PPA improvements. 

- Conduct formal verification.

1. SOC platform 架構與RTL implementation 

2. 負責 IP/子模組之 RTL 整合，組成 SoC (System-on-Chip) 或子系統的頂層設計。 

3. 依據設計規格，串接不同來源或平台的 RTL，確保各模組間介面相容與功能正確。 

4. 撰寫與維護整合 RTL 的頂層模組、配置腳本及連結測試環境。 

5. 針對整合後的設計進行功能模擬、靜態時序分析（STA）、Lint、CDC 及等驗證工作，並協助 debug。 

6. 與軟硬體、驗證、後端設計等團隊密切合作，確保整合流程順利與產品交付時程。 

7. 編寫設計文件及協助設計交付相關事務。

加入 MediaTek「先進製程平台 DFT」團隊，你的工作直接影響 N4/N3/N2 及更先進世代 Cloud ASIC 的可靠度與良率。  

- DFT 架構與插入：針對先進節點 SoC 及 chiplet/3D-IC 設計，定義並實作 Scan（full-scan、compressor）、MBIST、BSD/JTAG 架構；使用 Synopsys / Siemens (Tessent) EDA 工具執行端到端插入流程。  

- ATPG 與 Advanced Fault Model：開發並優化 stuck-at、transition delay、cell-aware、path-delay 等 fault model 的 ATPG pattern；驅動 fault coverage closure 並交付 DRC-clean pattern。  

- 模擬與驗證：透過 gate-level simulation（VCS/Xcelium）驗證 DFT 邏輯正確性；解決 DFT rule violation 與 coverage gap，確保 tapeout 品質。  

- 後矽驗證與測試：主導 CP / FT / HTOL / HVS 各階段 DFT 工作，包含 test mode 驗證、scan chain 連通性測試、MBIST 執行與 repair 確認。 - Volume Diagnosis 與 Yield Ramp：運用 scan/MBIST diagnosis 資料分離系統性缺陷，與製程及 FA 團隊協作加速 yield learning 與技術成熟。  

- RMA / DPPM 除錯：利用 DFT diagnosis 流程調查 field return，協助降低 DPPM 並防止 escape。  

- 產業前沿：持續追蹤 Cloud ASIC chiplet 測試趨勢、ATE 技術進展與 EDA 新功能，主動將新觀念帶入團隊。 

職務要求

Responsible for GPU HW development environment tool/flow maintenance and database (perforce) management. Effectively support DE/DV smooth development.

1. Work on AI development for design flow  

2. Perform floorplan, clock planning, place and route, timing closure, ECO, IR signoff flow automation