電源管理IC應用工程師

Multi-RAT (6G/5G/4G/3G/2G) modem development. This is a common job description. You may involve at least one or more topics in the following: 

(1) architecture planning 

1.1 Modem/SoC TOP system architecture 

1.2 Modem/SoC CPU system design 

1.3 Modem/SoC DSP system design 

1.4 Modem/SoC BUS system design 

(2) digital circuit design and verification 

2.1 baseband modules 

2.2 digital front-end modules 

2.3 RF/mixed-mode digital control modules 

2.4 Computer/network system modules 

2.5 High speed interface design 

(3) IP integration 

3.1 Clock/reset, test modeand low power mode design 

3.2 floorplan and synthesis development 

(4) Design methodology 

4.1 design flow enhancement (low power/verification/etc) 

4.2 chip MP quality control flow

1. 5G modem 架與數位電路設計 

2. CLK, 測試, Reset相關設計與規劃 

3. 低功耗設計 

4. 系統整合 RTL 到 Gate level, 含STA

Design the 5G and next-generation modem processor with cost effective, high speed, and low power hardware performance. This position will develop the modem processor that optimized for modem system. Co-work closely with software and system architecture colleague to analysis the sweet point of system performance and low power. In this position, you will push the physical performance to next level and co-work with place-and-route (PAR) team resolving the bottleneck of speed and power.

-規劃並執行高速介面（如 PCIe, USB, DP, UFS, CSI, UCIe）IP PHY 驗證。 

-建立並維護測試平台，進行 System 與 Electrical 測試。 

-使用 Scope, BERT, LA, Signal Analyzer 等儀器進行 Signal Integrity 與 Compliance Test。 

-分析測試結果，協助 DE 及 SW 團隊解決問題。 

-設計並開發硬體 PCB 評估板，支援系統驗證。

As deep sub-micron process requires longer research cycle and higher manufacture cost, DV(design verification) has become an inevitable part of design group in Mediatek chip development flow. 

CDG DV is in charge of development and implementation of smart phone, TV, and ASIC product line verification plan.  

It included: integrated simulation/verification env development, big data analysis and efficiency improvement, bus fabric / EMI (External memory interface ) / Low power functions verification plan and implementation  

Need to build up verification plan/bench and continuously improve methodology, and you will understand both detail scenario and global view of cell phone/ASIC operating schemes 

Need to leverage the latest EDA tool and concept to accomplish the verification plan 

Work location: Hsinchu/Taipei

(請留意：為加快面試安排時間，僅限定投遞5個職缺)我們在找這樣的你：對行動通訊、無線及寛頻連結、家庭娛樂晶片解決方案有濃厚興趣；勇於表達意見，以團隊成功為目標，面對困難不輕易放棄，總是在想更好的做法，擁有創新及不斷學習的精神。聯發科技邀請您，與全球最頂尖的菁英一同合作，彼此激盪最新的創意與解法，共同挑戰每一個不可能。

1. SoC IC implementation 規劃設計 

2. DFT 規劃設計 以及timing closure signoff 

3. 設計方法流程開發及優化 

4. 工作地點:新竹/台北

1. Own the top-level integration of internal and third-party IPs into SOC or FPGA platform. 

2. Ensure interface compatibility, clock/reset domain correctness. Resolve integration issues including timing, CDC/RDC, and floorplan. 

3. Work closely with architect to define specification, support physical design team through synthesis constraints and integration guidance, partner with firmware and validation teams to ensure smooth bring-up and validation.

1. 數位 IC 設計 

2. 高速 Ethernet PCS/RSFEC/MAC 設計 

3. 高速電路架構與整合

1. Serdes PMA IP architecture planning 

2. Serdes PMA IP RTL coding 

3. Serdes PMA IP front-end and back-end integration 

4. Co-work with PCS and MAC design team and DV team for IP verification 

5. Co-work with Analog design team for PHY co-simulation 

6. Co-work with Algorithm team for algorithm implementation and bit-true verification

1. 熟悉 2.5D 或是 3D 封裝技術, 開發和量產經驗  

2. 從系統架構優劣比較, SIPI 或是測試或是 thermal 角度來提供適合的封裝技術

1. Develop 3.5D methodology from RTL to GDS and Package 

2. Coordinate Thermal and PI/SI team to deal with high power design 

3. Execute the project at different phases

1. 整合IR 資訊和內部團隊合作解決 IR 問題 

2. 產生並分析 power 資訊 

3. 和客戶溝通 IR 相關的 methodology 並開發流程解決問題

1. 數位晶片設計流程與整合  

2. 熟悉低功耗的設計流程(和架構)

1. Develop and implement DRAM controller/PHY solutions for data-center applications. Validate functionality, improve design to optimize performance, power, latency and efficiency. 

2. Memory controller/PHY Integration: Design and integration memory system.

• Chip to Chip 介面類比 PHY 電路，例如 UCIe 標準或客製化的 Die to Die 連結類比電路設計 

• HBM/DDR/LPDDR類比PHY電路設計與混合模式/高速電路設計等。

We are looking for a Senior DFT Engineer to define and implement DFT architectures for data center ASIC products. The role involves developing test strategies, integrating DFT features, and improving test coverage for mass production. You will work closely with design teams to ensure robust DFT solutions, yield improvement, and quality.  

Key Responsibilities 

• Develop and optimize test strategies to achieve coverage and manufacturing goals; analyze and improve test coverage. 

• Integrate DFT features at RTL and gate-level, supporting both top and block-level DFT planning and implementation. 

• Perform ATPG, fault simulation, and coverage analysis. 

• Collaborate with BE and PD teams to ensure DFT-friendly timing and support IR convergence in test mode. 

• Lead silicon bring-up and debug of test features; conduct failure and yield analysis. 

• Work with product teams to facilitate pattern generation, validation, and DPPM improvement.

1. 旗艦智慧型手機晶片整合  

2. 車用系統晶片整合  

3. Clock架構  

4. Timing收斂與分析  

5. DFT/Test mode整合驗證

1. Architecture design and RTL implementation of Automotive/Smartphone chipset 

2. SoC system power and performance analysis 

3. SoC system bus and memory subsystem design, integration, and modeling 

4. SoC low power design, integration, and modeling 

5. SoC functional safety analysis, design, integration, and modeling 

6. SoC cyber security analysis, design, integration, and modeling

車用相關 IC 設計流程專家。 具備車用SoC/ASIC RTL2GDS 實做經驗和問題解決能力。 同時具備車用IC設計流程中 Safety mechanism 的專業知識。