電源管理IC應用工程師

1. Architecture design and RTL implementation for Smartphone and automotive chip 

2. Smartphone SoC and mobile computing platform design.  

3. System bus and high speed interface designs

We are seeking a highly skilled DFT/DFM Engineer to join our automotive ADAS SoC chip design team.  

The successful candidate will be responsible for DFT and DFM methodologies, design, and implementation for our advanced automotive system-on-chip (SoC) designs.  

The candidate will also collaborate with the design and layout teams to integrate DFT/DFM requirements. 

• SoC testing architecture design  

• Support project NPI(new product introduction) to MP(mass production) (test program development, coverage enhancement, yield improvement, cost reduction) 

• Cowork w/ IP, test engineer, process team, board design to fulfill CP/FT/SLT test requirement.

1. Smartphone (Low Power Architect) and Automotive (Power control) 

2. Not a management position 

3. Short term:digital IP design/integration of power control IPs with zero bugs  

Long term:define power control arch for smartphone or automotive products 

develop new tech for power control

1. Develop and implement tailored DRAM controller/PHY solutions for automotive applications. Validate functionality, improve design revisions and meet performance targets as well as system requirements. 

2. Perform rigorous design testing and debugging in automotive environments. Troubleshoot and propose solutions for any issues occurring in post-silicon validation. 

3. System Level Cache Design & Implementation: Design and implement system level cache strategies to optimize performance and efficiency across our product range. 

4. System-Level Understanding: Exhibit a system-level understanding of performance trade-offs, system architecture, memory subsystems, and various memory technologies (DDR3, DDR4, DDR5, LPDDR3, LPDDR4, LPDDR5 etc.). 

5 . Ensure that all designs comply with automotive industry standards and regulations, such as ISO 26262 and Automotive SPICE.

1. Develop high speed interface subsystem architecture and integrate PCIe, MIPI, or DisplayPort subsystem. 

2. Develop security and FuSa function on PCIe, MIPI, or DisplayPor degital circuit.

解讀客戶的網絡安全需求 

從網絡安全需求中推導出功能和安全概念 

制定和審查安全系統架構 

與 IP 團隊和客戶溝通和協調安全設計 

執行系統安全分析（例如：TARA）

1. Interpret customers’ functional safety requirements 

2. Derive functional and technical safety concepts from functional safety requirements 

3. Develop and review the safety IP design 

4. Communicate and coordinate safety designs with IP teams 

5. Perform system safety analysis (ex: FMEDA)

1. Interpret customers’ functional safety requirements into SoC requirements 

2. Define the SoC level architectures to meet functional safety requirements 

3. Communicate and coordinate safety designs with cross-function IP teams 

4. Perform system safety analysis (ex: FMEDA)

1.數位電路設計  

2.多媒體架構與電路設計  

3.多媒體系統整合 

1.Digital IC Design 

2.Multimedia Architecture and Design 

3.Multimedia System Integration

Wi-Fi架構和數位電路設計 

整個晶片的時鐘、測試和重置規劃 

低功耗數位設計 

從RTL到閘級的SoC晶片整合，包括時序收斂和可測試性 

設計方法和整合流程改進

1. Processor core, cache and peripheral verification 

2. Verification flow and methodology 

3. Advanced tool and verification technology survey

1. Serdes/High speed interface related PHYD IP architecture planning. 

2. Serdes/High speed interface related PHYD IP RTL coding.  

3. Serdes/High speed interface related PHYD IP front-end and back-end integration.  

4. Co-work with MAC design team and DV team for IP verification.  

5. Co-work with Analog design team for PHY co-simulation.

Requirements Elicitation, Requirements Analysis, and Architectural Design 

- Analyze product requirements from customer 

- Discuss the expectations and requests with customer 

- Agree or reject the requirements 

- Make architectural design proposals

對於DFT晶片測試有興趣者，特別是 Automotive low DPPM DFT 以及 RISC-V DFT 領域， 

負責開發與實行DFT流程，以降低測試成本、提高產品品質為目的 

As a member of DFT engineering team, the candidate will develop methodologies and implement DFT for pre/post-silicon DFT flow and contribute to Automotive/RISC-V product test quality. 

Work with senior engineers across disciplines (DE, IMP, PE, TE) to meet low cost and high quality testing

1. DFT architecture exploration & evaluation for next-gen process node & package technology of MediaTek: 

* Scan chain insertion & ATPG pattern generation 

* Pattern validation through simulation & silicon analysis(pass/fail, shmoo, fail log, etc.) 

* Diagnosis to help manufacture process improvement 

2. Co-work with SoC architect, RTL designer, physical design engineer, and package engineer to define best architecture for 3D-IC: 

* PPA(Performance/Power/Area) impact analysis & mitigation via DFT innovation 

* Develop & integrate DFT-related RTL design modules to test chip

Fully accountable with the team to deliver highly competitive ARM based CPU IP. Implementation skill required ranged from RTL, synthesis, DFT, Floorplan, Placement, CTS, Routing, Timing Closure, and physical verification.

We are looking for AI hardware architect/designer to join our team and play a pivotal role in designing, developing, and optimizing architecture of the neural processing unit (NPU). As an architect/designer, you will be responsible for creating innovative hardware and software solutions that meet the performance, scalability, and efficiency requirements of our advanced NPU environment. The ideal candidate will have a strong background in computer architecture, microarchitecture, and digital design, as well as experience with industry-standard tools and methodologies. You are expected to transform novel ideas into practical proposals for future NPU products, and vet the proposals via prototyping. Extensive knowledge in compiler and operating system is a plus. International travel may be required.

影像編碼器硬體架構規劃與電路設計實現

(請留意：為加快面試安排時間，2026校招僅限定投遞5個職缺)我們在找這樣的你： 資工/資管/電子/電機/電信/通訊/電控相關研究所背景，對行動通訊、無線及寛頻連結、家庭娛樂晶片解決方案有濃厚興趣的2026年應屆畢業生。 勇於表達意見，以團隊成功為目標，面對困難不輕易放棄，總是在想更好的做法，擁有創新及不斷學習的精神。 聯發科技邀請您，與全球最頂尖的菁英一同合作，彼此激盪最新的創意與解法，共同挑戰每一個不可能。

(請留意：為加快面試安排時間，2026校招僅限定投遞5個職缺)我們在找這樣的你： 資工/資管/電子/電機/電信/通訊/電控相關研究所背景，對行動通訊、無線及寛頻連結、家庭娛樂晶片解決方案有濃厚興趣的2026年應屆畢業生。 勇於表達意見，以團隊成功為目標，面對困難不輕易放棄，總是在想更好的做法，擁有創新及不斷學習的精神。 聯發科技邀請您，與全球最頂尖的菁英一同合作，彼此激盪最新的創意與解法，共同挑戰每一個不可能。